Intel Corporation

Ruitao Zhang

Bruce A Block

Richard Scott List

Justin K Brask

Mohamed A Shaheen

On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. On-chip decoupling capacitors help to reduce or prevent L di/dt voltage droop on the power grid for high surge current conditions. The inclusion of one or more decoupling capacitors on a chip, in close proximity to the power grid conductors reduces parasitic inductance and thereby provides improved decoupling performance with respect to high frequency noise. In one embodiment of the present invention, a capacitor stack structure is inserted between metal interconnect layers. Such a capacitor stack may consist of a bottom electrode/barrier; a thin dielectric material having a high dielectric constant; and a top electrode/barrier. In an alternative embodiment, the bottom electrode and/or bottom metal interconnect layer have three dimensional texture to increase the surface area of the capacitor. An illustrative method embodying the present invention, includes fabricating the on-chip decoupling capacitor stack structure and electrically connecting the capacitor to provide efficient capacitive de-coupling. In order to facilitate the removal of photoresist by an oxygen plasma process prior to exposing copper conductors during the capacitor stack etch, an Al hardmask can be used to protect the capacitor formed with TaOdielectric, or a W hardmask can be used to protect the capacitor formed with BST dielectric.

Method of forming on-chip decoupling capacitor with bottom electrode layer having surface roughness

An improvement in the method of fabricating on chip decoupling capacitors which help prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. The inclusion of a hybrid metal/metal nitride top electrode/barrier provides for a low cost and higher performance option to strapping decoupling capacitors.

Top electrode barrier for on-chip die de-coupling capacitor and method of making same

The present invention discloses a method including: providing a silicon wafer; forming a buried oxide (BOX) in the silicon wafer below a silicon body; and reducing a thickness of the silicon body by chemical thinning.

Chemical thinning of silicon body of an SOI substrate

Method of forming on-chip decoupling capacitor by selectively etching grain boundaries in electrode

Chemical thinning of epitaxial silicon layer over buried oxide

On-chip decoupling capacitor structures, and methods of fabricating such decoupling capacitors are disclosed. In one embodiment of the present invention, a capacitor stack may consist of a bottom electrode/barrier; a thin dielectric material having a high dielectric constant; and a top electrode/barrier. In an alternative embodiment, the bottom electrode and/or bottom metal interconnect layer have three dimensional texture to increase the surface area of the capacitor. An illustrative method embodying the present invention, includes fabricating the on-chip decoupling capacitor stack structure and electrically connecting the capacitor to provide efficient capacitive de-coupling.

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Portland, OR, United States of America

Ruitao Zhang