Freescale Semiconductor,inc.

Motorola Corporation

Amd Inc.

Ruiqi Tian

Edward Outlaw Travis, Jr

Omar Zia

Sejal N Chheda

Mehul D Shroff

Venkat Kolagunta

Nigel Graeme Cave

Bradley Paul Smith

Tat-Kwan Edgar Yu

Aykut Dengi

James Derek Legg

Terry Alan Breeden

David M Schraub

Nathan A Aldrich

Mark S Roberton

Kevin John Hess

Trent Uehling

Brett P Wilkerson

Scott K Pozder

Willard E Conley

Alfred J Reich

Robert Elliott Boone

Katie C Yu

Thomas Michael Brown

A method for making a semiconductor device is provided which comprises (a) creating a first mask for the epitaxial growth of features in a semiconductor device, said first mask defining a set of epitaxial tiles (); (b) creating a second mask for defining the active region of the semiconductor device, said second mask defining a set of active tiles (); and (c) using the first and second masks to create a semiconductor device.

Integrated assist features for epitaxial growth

A method for making a semiconductor device is provided which comprises (a) creating a data set () which defines a set of tiles for a polysilicon deposition process; (b) deriving a polysilicon deposition mask set () from the data set, wherein the polysilicon deposition mask set includes a plurality of polysilicon tiles (); (c) deriving an epitaxial growth mask set () from the data set, wherein the epitaxial growth mask set includes a plurality of epitaxial tiles (); and (d) using the polysilicon deposition mask set and the epitaxial growth mask set to make a semiconductor device (); wherein the epitaxial growth mask set is derived from the data set by using at least a portion of the tile pattern defined in the data set for at least a portion of the tile pattern defined in the epitaxial deposition mask set.

A semiconductor process and apparatus to provide a way to reduce plasma-induced damage by applying a patterned layer of photoresist which includes resist openings formed over the active circuit areas as well as additional resist openings formed over inactive areas in order to maintain the threshold coverage level to control the amount of resist coverage over a semiconductor structure so that the total amount of resist coverage is at or below a threshold coverage level. Where additional resist openings are required in order to maintain the threshold coverage level, these openings may be used to create additional charge dissipation structures for use in manufacturing the final structure.

Method for reducing plasma discharge damage during processing

A semiconductor process and apparatus to provide a way to reduce plasma-induced damage by applying a patterned layer of photoresist () which includes resist openings formed () over the active circuit areas () as well as additional resist openings () formed over inactive areas () in order to maintain the threshold coverage level to control the amount of resist coverage over a semiconductor structure so that the total amount of resist coverage is at or below a threshold coverage level. Where additional resist openings () are required in order to maintain the threshold coverage level, these openings may be used to create additional charge dissipation structures (e.g.,) for use in manufacturing the final structure.

A method for forming a semiconductor device includes providing a semiconductor substrate having a first region and a second region. The first region has one or more first elements and the second region has one or more second elements. The first elements are different from the second elements. A tile location and a first tile surface area for a tile feature on the semiconductor device is defined. An active semiconductor layer is formed over both the first region and the second region of the semiconductor substrate. A first trench is formed in the active semiconductor layer at the tile location using a negative tone mask. The first trench has a first depth and forms at least a portion of the tile feature. A second trench is formed in the active semiconductor layer using a positive tone mask. The second trench has a second depth different than the first depth.

Semiconductor device having tiles for dual-trench integration and method therefor

A method for forming a semiconductor device includes providing a plurality of features in a layout, selecting critical features from the plurality of features, placing a first plurality of short-range dummy etch features in the layout at a first distance from the critical features to increase the feature density near the critical features, wherein each of the first plurality of short-range dummy etch features has a first width, removing at least one of the first plurality of short-range dummy etch features from the layout that will subsequently interfere with the electrical performance of at least one active feature so that a second plurality of short-range dummy etch features remains, and using the layout to pattern a layer on a semiconductor substrate.

Method of forming a semiconductor device having dummy features

A method for making a semiconductor device is provided which comprises (a) creating a first data set () which defines a first set of tiles () for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set () and a first epitaxial growth mask set () from the first data set, wherein the first epitaxial growth mask set is derived from the first data set by removing a subset () of the tiles defined by the first data set and incorporating the subset of tiles into the first epitaxial growth mask set; and (c) reconfiguring the first trench CMP mask set to account for the first epitaxial growth mask set, thereby defining a second trench CMP mask set ().

Integrated assist features for epitaxial growth bulk tiles with compensation

A method for making a semiconductor device is provided which comprises (a) creating a first data set () which defines a first set of tiles () for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set () and at least one epitaxial growth mask set () from the first data set, wherein the at least one epitaxial growth mask set corresponds to tiles () present on first () and second () distinct semiconductor surfaces; (c) reconfiguring the first trench CMP mask set to account for the at least one epitaxial growth mask set, thereby defining a second trench CMP mask set (), wherein the second trench CMP mask set defines a set of trench CMP tiles; and (d) using the second trench CMP mask set to make a semiconductor device.

Integrated assist features for epitaxial growth bulk/SOI hybrid tiles with compensation

A method for identifying areas of low overburden which degrade (increase) metal polish nonuniformity is discussed. Also described is a method for modifying these areas to increase their overburden, thus slowing down the metal polish rate and improving overall polish uniformity. The resulting structure forms slots in groups of functional lines, such as bus lines, when the functional lines have a density prior to forming the slots that exceeds a predetermined amount. In one embodiment, an area of the wafer has a maximum width of 1.5 microns in an area that has a feature density greater than approximately 50 percent. The methods and resulting structures create a higher feature density, thereby increasing polishing uniformity.

Method of implementing polishing uniformity and modifying layout data

An integrated circuit has metal bumps on the top surface that create a potentially destructive stress on the underlying layers when the metal bumps are formed. Ensuring a minimum metal concentration in the underlying metal interconnect layers has been implemented to reduce the destructive effect. The minimum metal concentration is highest in the corners, next along the border not in the corner, and next is the interior. The regions in an interconnect layer generally under the metal bump require more concentration than adjacent regions not under a bump. Lesser concentration is required for the metal interconnect layers that are further from the surface of the integrated circuit. The desired metal concentration is achieved by first trying a relatively simple solution. If that is not effective, different approaches are attempted until the minimum concentration is reached or until the last approach has been attempted.

Die level metal density gradient for improved flip chip package reliability

In a feature layer of a semiconductor wafer, dummy tiles which overcome the tendency of dishing and erosion to occur during a CMP process are placed with various sizes and in various positions. An isolation zone is provided around active features. A scanning process of the feature layout surveys oxide density and nitride density over the wafer layer outside of said isolation zone. Values of the ratios of oxide/nitride density for two or more length scales which define tiling zones, are calculated. Tile placement and sizing in the zones is dependent upon the oxide/nitride density ratio values; and further upon an oxide deposition model specific to the oxide used in the fabrication process and upon a polishing model of the CMP process being employed.

Method for improving planarity of shallow trench isolation using multiple simultaneous tiling systems

A method for forming an integrated circuit device having dummy features and the resulting structure are disclosed. One embodiment comprises a first active feature separated from a substantially smaller second active feature by a dummy-available region void of active features. Within the dummy-available region and in close proximity to the second active feature exists a dummy feature.

Method of forming an integrated circuit device using dummy features and structure thereof

Selective placement of polishing dummy feature patterns, rather than indiscriminate placement of polishing dummy feature patterns, is used. Both low frequency (hundreds of microns and larger) and high frequency (10 microns and less) of topography changes are examined. The polishing dummy feature patterns can be specifically tailored to a semiconductor device and polishing conditions used in forming the semiconductor device. When designing an integrated circuit, polishing effects for the active features can be predicted. After polishing dummy feature pattern(s) are placed into the layout, the planarity can be examined on a local level (a portion but not all of the device) and a more global level (all of the device, devices corresponding to a reticle field, or even an entire wafer).

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Austin, TX, United States of America

Ruiqi Tian