Mentor Graphics Corporation

Synopsys, Inc.

Other

Synopsis Incorporated

Ruifeng Guo

Wu-Tung Cheng

Yu Jane Huang

Liyang Lai

Brian Archer

Ting-Pu Tai

Xiaolei Cai

Yu Hu

Manish Sharma

Kun-Han Tsai

Jing Ye

Kevin Chau

Emil I Gizdarski

Martin Keim

Ronald Press

Etienne Racine

Takeo Kobayashi

William Albert Lloyd

Christopher Kevin Allsup

Systems and methods disclosed include receiving defect data from a test of a semiconductor device comprising a circuit, the circuit comprising a cell, the cell comprising a first input, a second input and an output, and modeling a first plurality of cell defect modes of the cell with a first multiple input transition cell fault model (MTCFM), the cell defect modes associated with a first signal transition on the first input, and a second signal transition on the second input or the output. Systems and method further include correlating the first plurality of cell defect modes to the defect data to produce a probability of each of the first plurality of cell defect modes matching the defect data, and providing, to a user, an indication of each of at least one of the first plurality of cell defect modes having the probability exceeding a defect probability threshold.

Adaptive cell-aware test model for circuit diagnosis

To specifically identify faults within a semiconductor cell, a SPICE netlist associated with the semiconductor cell design is retrieved, and one or more transistor characteristics are identified within the SPICE netlist. An advanced cell-aware fault model is executed for the semiconductor cell, and results are returned for one or more fault test methods of the advanced cell-aware fault model for a cell of the semiconductor chip design. A method for identifying faults within the semiconductor cell continues by correlating one more faults detected as a result of the fault test methods with one or more transistor characteristics within the SPICE netlist, and a user interface is generated for identifying one or more faulty transistors within the semiconductor chip design.

Advanced cell-aware fault model for yield analysis and physical failure analysis

Disclosed is cell-aware defect characterization by considering inter-cell timing. Also disclosed is a method and apparatus that determines whether a defect can be detected in a standard library cell used to design an integrated circuit. A defect detection table is generated that indicates whether particular defects can be detected with particular combinations of input logic states and under varying load conditions. Results are merged to provide a single metric for each combination of input and output logic states that indicates one of three possible results for each defect: (1) whether the defect can be detected under all load conditions, (2) whether the defect can be detected only under some load conditions; or (3) whether the defect cannot be detected for the particular combination of input logic states regardless of the load conditions.

Cell-aware defect characterization by considering inter-cell timing

A cell-aware defect characterization method includes partitioning a multibit cell netlist file into multiple single-bit partition netlist files, and then generating a cell-aware test model for each partition netlist file. Partitioning is performed such that each partition netlist file includes a corresponding flip-flop along with input, output and control pins that are operably coupled to the input, output and control terminals of the corresponding flip-flop, and all active, passive and parasitic circuit elements that are coupled in the signal paths extending between the corresponding flip-flop and the input/output/control pins. Shared resources (e.g., clock or scan select pins and associated signal lines) that are utilized by two or more flip-flops are included in each associated partition. The partitioning process is performed using either a structural back-tracing approach or a logic simulation approach.

Cell-aware defect characterization for multibit cells

A computer-implemented method for characterizing a circuit is presented. The method includes receiving, by the computer, data representative of the circuit and at least one defect of the circuit. The method further includes simulating, using the computer, the circuit to obtain a first timing characteristic, and simulating, using the computer, the circuit with the at least one defect to obtain a second timing characteristic. The method further includes identifying, using the computer, an association between at least one test vector and the at least one defect in accordance with the first timing characteristic, the second timing characteristic, and a multitude of strobes applied during a first time interval associated with the at least one test vector, when the computer is invoked to characterize the circuit.

Cell-aware defect characterization and waveform analysis using multiple strobe points

Embodiments of the disclosed technology comprise software-based techniques that can be used to improve scan chain test pattern generation and scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to a single scan cell. Such embodiments can be used to generate a 'complete' test set&#x2014;that is, a set of chain diagnosis test patterns that is able to isolate any scan chain defect in a faulty scan chain to a single scan cell.

Generating test sets for diagnosing scan chain failures

Aspects of the invention relate to test access architecture for stacked memory and logic dies. A test access interface for a logic die that is stacked under a memory die is disclosed. The disclosed test access interface can control testing logic core, interconnections with the memory die and with another logic die. The controlling of testing interconnections with the memory die is through a memory boundary scan register controller in the test access interface.

Test access architecture for stacked memory and logic dies

The disclosed ring-oscillator-based test architecture comprises a plurality of boundary scan cells coupled to a plurality of interconnects and control circuitry. Each of the plurality of boundary scan cells can be configured to operate as, based on control signals, a conventional boundary scan cell or any bit of an asynchronous counter. The control signals are supplied by the control circuitry.

Test architecture for characterizing interconnects in stacked designs

Aspects of the invention relate to techniques of using two-dimensional scan architecture for testing and diagnosis. A two-dimensional scan cell network may be constructed by coupling input for each scan cell to outputs for two or more other scan cells and/or primary inputs through a multiplexer. To test and diagnose the two-dimensional scan cell network, the two-dimensional scan cell network may be loaded with chain patterns and unloaded with corresponding chain test data along two or more sets of scan paths. Based on the chain test data, one or more defective scan cells or defective scan cell candidates may be determined.

Two-dimensional scan architecture

A dictionary-based scan chain fault detector includes a dictionary with fault signatures computed for scan cells in the scan chain. Entries in the fault dictionary are compared with failures in the failure log to identify a faulty scan cell. In one embodiment a single fault in a scan chain is identified. In another embodiment, a last fault and a first fault in a scan chain are identified.

Fault dictionary based scan chain failure diagnosis

A diagnosis technique to improve scan cell internal defect diagnostic resolution using scan cell internal fault models.

Detection and diagnosis of scan cell internal defects

Aspects of the invention relate to techniques for cycle-based scan chain diagnosis for integrated circuits with embedded compactors. With various implementations of the invention, no-failing-bits output channels of a compactor are first identified based on output data of a test. Next, good scan chains are identified based on scan chains associated with the no-failing-bits output channels. From scan chains other than the good scan chains, analysis of bits outputted from failing-bits output channels per clock cycle is performed to identify suspected faulty scan chains.

Faulty chains identification without masking chain patterns

Aspects of the invention relate to techniques for determining scan chains that could be diagnosed with high resolution. A circuit design and the information of scan cells for the circuit design are analyzed to determine information of potential logic relationship between the scan cells. The information of potential logic relationship between the scan cells may comprise information of fan-in cones for the scan cells. Based at least in part on the information of potential logic relationship between the scan cells, scan chains may be formed. The formation of scan chains may be further based on layout information of the circuit design. The formation of scan chains may be further based on compactor information of the circuit design.

Diagnosis-aware scan chain stitching

Aspects of the invention relate to techniques for diagnosing compound hold-time faults. A profiling-based scan chain diagnosis may be performed on a faulty scan chain to determine observed scan cell failing probability information and one or more faulty segments based on scan pattern test information. Calculated scan cell failing probability information may then be derived. Based on the calculated scan cell failing probability information and the observed scan cell failing probability information, one or more validated faulty segments are verified to have one or more compound hold-time faults. Finally, one or more clock defect suspects may be identified based on information of the one or more validated faulty segments.

Growing community of inventors

Portland, OR, United States of America

Ruifeng Guo