Lucent Technologies Inc.

At+t Corp.

At&t Bell Laboratories

Agere Systems Inc.

Ruichen Liu

Chun-Ting Liu

Kuo-Hua Lee

Sungho Jin

Wei Zhu

William T Lynch

Chien-Shing Pai

Philip W Diodato

Alvaro Maury

Ronald J Schutz

Glenn B Alers

Steven J Hillenius

Kin Ping Cheung

James Thomas Cargo

Joseph Lebowitz

Richard S Wagner

David S Williams

Christopher J Case

Michael G Thomson

Chorng-Ping Chang

Ronald James Holmes

An integrated circuit includes a semiconductor substrate with semiconductor devices formed therein and thereon, a first wiring layer located over the substrate, a second wiring layer located on the first wiring layer, and a capacitor. The capacitor has metal-based charge-storage electrodes that extend through the second wiring layer and at least part of the first wiring layer. The wiring layers have interconnect wire embedded therein.

Inter-wiring-layer capacitors

A process for fabricating trench capacitors in an interconnect layer of a semiconductor device is disclosed. In the process, at least one interconnect is formed in the interconnect layer, which is then planarized. To form the trench capacitor, a trench is formed in the dielectric material of the interconnect. The bottom of the trench communicates with a metal contact in the underlying layer. A barrier layer of material is formed on the interconnect layer and is anisotropically etched, leaving the barrier layer on the sidewalls of the trench. The lower plate of the capacitor is then formed by depositing a layer of metal over the interconnect layer. The layer of metal is then anisotropically etched, removing the metal on the surface of the interconnect layer and leaving the metal along the trench perimeter. The capacitor dielectric layer is then deposited over the interconnect layer and subsequently patterned. Another layer of barrier material is deposited on the interconnect layer. The metal for the top plate of the capacitor is then deposited over the interconnect layer. The top plate of the capacitor extends into the trench. The metal layer and barrier layer are then patterned to form the top plate of the capacitor.

Process for fabricating an integrated circuit device having capacitors with a multilevel metallization

The invention provides a device containing a low .kappa., hydrogen-free a-C:F layer with good adhesion and thermal stability. It was found that the combination of desirable properties was attainable by a relatively easy process, as compared to processes that utilize gaseous sources, such as CVD. Specifically, the a-C:F layer is formed by sputter deposition, using only solid sources for the fluorine and carbon, and in the absence of any intentionally-added hydrogen-containing source. The sputtering is performed such that the layer contains 20 to 60 at. % fluorine, and also, advantageously, such that the a-C:F exhibits a bandgap of about 2.0 eV or greater. The a-C:F layer formed by the process of the invention exhibits a dielectric constant, at 1 MHz and room temperature, of 3.0 or less, advantageously 2.5 or less, along with being thermally stable up to at least 350.degree. C., advantageously 450.degree. C., and exhibiting a stress of about 100 MPa or less, in absolute value.

Article comprising fluorinated amorphous carbon and method for

The invention provides a device containing a low .kappa., hydrogen-free a-C:F layer with good adhesion and thermal stability. It was found that the combination of desirable properties was attainable by a relatively easy process, as compared to processes that utilize gaseous sources, such as CVD. Specifically, the a-C:F layer is formed by sputter deposition, using only solid sources for the fluorine and carbon, and in the absence of any intentionally-added hydrogen-containing source. The sputtering is performed such that the layer contains 20 to 60 at. % fluorine, and also, advantageously, such that the a-C:F exhibits a bandgap of about 2.0 eV or greater. The a-C:F layer formed by the process of the invention exhibits a dielectric constant, at 1 MHz and room temperature, of 3.0 or less, advantageously 2.5 or less, and more advantageously 2.1 or less, along with being thermally stable up to at least 350.degree. C., advantageously 450.degree. C., and exhibiting a stress of about 100 MPa or less, in absolute value.

Article comprising fluorinated amorphous carbon and process for

A method of manufacturing integrated circuits utilizing chemical mechanical polishing (CMP) is disclosed. A dielectric layer, illustratively, having a dopant, dye, etc. termed a 'marker layer' is formed upon a wafer having partially fabricated integrated circuits thereon. An undoped, undyed layer is deposited upon the marker layer. The undoped or undyed layer is polished and the waste slurry is monitored until a signal indicating the exposure of the signal layer is obtained. Analysis of the signal provides an indication of when the CMP process should be terminated.

Method of mechanical polishing

A method for fabricating a multi-level integrated circuit is disclosed which utilizes a grid pattern from which portions corresponding to the metal layer are selectively removed to form a mask which is subsequently used to deposit dummy features in the open areas between metal lines, thereby to allow the deposition of a substantially planar dielectric surface over the metal layers and dummy features.

Process for producing multi-level metallization in an integrated circuit

An integrated circuit device having reduced-height gate stack is fabricated by using a patterned oxide hard mask to pattern the underlying metal layer. The oxide mask is removed and the patterned metal is subsequently used as a mask to etch the polysilicon layer.

Method of fabricating gate stack having a reduced height

A field effect transistor is fabricated with an ion implanted silicide layer and a conducting diffusion barrier pad layer that acts as a diffusion mask. The dopants from the silicide layer are diffused into the substrate to form shallow source/drain regions.

Method of making field effect transistor with a sealed diffusion junction

A field effect transistor is fabricated with a window pad layer that is patterned using a patterned dielectric with sublithographic spacing as an etch mask. Desirable attributes of the transistor include small junction capacitance.

Field effect transistor with landing pad

Shallow junctions n- and p-channel field effect transistors are formed with a single ion implant into a conformal tungsten silicide layer. Although phosphorous and boron are implanted into the same silicide regions, the phosphorous prevents the boron from outdiffusing.

Method of manufacturing shallow junction field effect transistor

In CMOS based integrated circuits, stricter design rules require source and drain junctions shallower than 2500 .ANG.. By using a specific device configuration, a shallow junction is obtainable while resistance to latch-up is improved and other electrical properties, e.g., low leakage current, are maintained. To achieve this result the p-channel device should have an activation energy of the junction reverse leakage current region less than 1.12 eV, with a junction dopant region shallower than 1200 .ANG. and a monotonically decreasing junction dopant profile.

Devices having shallow junctions

Direct contact to shallow junctions in integrated circuits and interconnection between these contacts is achievable by utilizing a specific aluminum CVD process. In this process the aluminum is deposited utilizing a triisobutyl aluminum precursor onto a substrate having a nucleation layer, e.g. a titanium nitride layer. By appropriate choice of this nucleation layer to control the nucleation of the depositing aluminum, suitable contact is made while avoiding void defects present in the absence of such layer.

Process for fabricating integrated circuits having shallow junctions

A new method for fabricating a semiconductor device, e.g., a MOS or MES IC, as well as the resulting device, are disclosed. In accordance with the new method, a semiconductor device is formed, at least in part, by forming a material region which includes metal, e.g., elemental metal or a metal-containing compound, on a semiconductor substrate. One or more dopants are implanted into the material region, and the substrate is heated in order to diffuse the dopants out of the material region and into the substrate, thus forming a dopant-diffused substrate region, e.g., a source or drain. Significantly, the new method involves implant conditions which yield a material region-to-substrate specific contact resistance equal to or less than about 10.sup.-6 .OMEGA.-cm.sup.2. In addition, the new method involves heating temperatures and heating times which yield a dopant-diffused substrate region having a depth, relative to the top of the material region, equal to or less than about 0.2 micrometers.

Method for fabricating semiconductor devices which include sources and

An electron emission system includes a high-brightness field-emitter cathode. Advantageously, the tip of the cathode is shaped to minimize structural variations caused by surface tension forces. In addition, an electrode assembly associated with the cathode is designed to establish electric field forces that are opposite and at least approximately equal to the surface tension forces acting on the tip. The electric field forces can be adjusted to establish a highly stable operating condition without altering the value of electron beam energy for which the overall system was designed. Moreover, the current density of the beam at a writing surface can be selectively varied without changing prescribed operating parameters of the cathode. The resulting system is characterized by excellent emission stability, low noise and a useful operating life of at least several thousand hours.

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Warren, NJ, United States of America

Ruichen Liu