Omnivision Technologies, Inc.

Samsung Electronics Co., Ltd.

Jiangsu University of Science and Technology

Zepp, Inc.

Acetec Semiconductor Co. Ltd.

Rui Wang

Tiejun Dai

Hiroaki Ebihara

Liang Zuo

Min Qu

Jianzhong Zhang

Zheng Yang

Yeqing Hu

Junmo Sung

Yang Li

Tianjia Sun

Xuelian Liu

Eiichi Funatsu

Zhiyong Zhan

Chengcheng Xu

Lihang Fan

Selcuk Sen

Xin Ru Wang

Chun-Ming Tang

Qingfei Chen

Chao-Fang Tsai

Wei Deng

Tiexing Wang

Shan Chen

Young-Han Nam

Keiji Mabuchi

Yaowu Mo

Liping Deng

Jin Yuan

Yu-Shen Yang

Qingwei Shan

Wei Wei Wang

Kenny Geng

Bi Yuan

Zhenfu Tian

Hiroki Ui

Nijun Jiang

Xueqing Wang

Sang Joo Lee

Chun-Sheng Yang

Boon Loong Ng

Chen Hui Xu

Dyson Hsinchih Tai

Sohei Manabe

Joseph W Yang

Jian Zhang

Guangbin Zhang

Lindsay Alexander Grant

Jian Guo

Gary Xu

Chin Poh Pang

Zhe Gao

Wenxian Tang

Woon Il Choi

Ling Fu

Takayuki Goto

Xiaodong Luo

Satoshi Sakurai

Olivier Bulteel

Shijie Su

Jun Yang

Wanqing Xin

Yongmei Zhu

Tao Sun

Yurong Xu

Sangjoo Lee

Da Meng

Jiayu Guo

Tomoyasu Tate

Baoji Yin

John Brummer

Chenyang Di

Shouvik Ganguly

Teijun Dai

Jing Yin

Yandong Chen

Le Huang

Zhengyu Li

Vivian Wang

Shaomin Ding

A pixel array includes a plurality of pixel cells, each including a photodiode configured to photogenerate image charge in response to the incident light, a first floating diffusion (FD) coupled to receive the image charge from the photodiode, a reset transistor coupled between a voltage source and the first FD, a second FD coupled between the first FD and ground, a first dual FD transistor coupled between the first and second FDs. Second FDs of first and second pixel cells are coupled. Second FDs of third and fourth pixel cells are coupled.

Triple conversion gain pixel

A method includes storing multiple signals received from a user equipment (UE) in a queue. The method also includes estimating a sounding reference signal (SRS) signal-to-noise-ratio (SNR) and determining a filtered SNR based on the received signals. The method also includes computing one or more features based on the filtered SNR and at least some of the received signals in the queue. The method also includes determining (i) a channel condition of the UE and (ii) a speed range of the UE based on the one or more computed features, wherein the channel condition of the UE comprises line-of-sight (LoS) or non-line-of-sight (NLoS). The method also includes determining a transmission configuration based on the channel condition of the UE and the speed range of the UE.

Low complexity machine learning based channel classifier

A local ramp buffer includes a deep N− well layer disposed in a P− substrate beneath a surface of the P− substrate, a P− well disposed between the surface of the P− substrate and the deep N− well layer, and an N− well structure disposed in the P− substrate and coupled to the deep N− well layer. The N− well structure is disposed between the surface of the P− substrate and the deep N− well layer. The P− well is disposed inside an opening in the N− well structure. The N− well structure and the deep N− well layer are configured to isolate the P− well within the opening. A source follower transistor is disposed in the P− well. The source follower transistor includes a gate terminal coupled to the N− well structure and a ramp generator.

Deep N-well driven ramp buffer

An imaging device includes a pixel array with 2×2 pixel circuits arranged in rows and columns. Each 2×2 pixel circuit includes 4 photodiodes. Bitlines are coupled to the 2×2 pixel circuits and a color filter array is disposed over photodiodes of the pixel array. The color filter array includes color filters having a first color, color filters having a second color, color filters having a third color. The photodiodes of each 2×2 pixel circuits are covered by one of the color filters. Photodiodes covered by color filters having the first color and photodiodes covered by color filters having the second color are configured to provide non-phase detection (non-PD) information. Photodiodes covered by color filters having the third color are configured to provide phase detection (PD) information. Half of the 2×2 pixel circuits have the photodiodes covered by color filters having the third color.

Phase detection auto focus with horizontal/vertical quad phase detection

A pixel cell readout circuit comprises a ramp generator having a ramp generator output. A first gain network is coupled to the ramp generator output and configured to provide a first variable comparator gain. A second gain network is coupled to the ramp generator output and configured to provide a second variable comparator gain. A first comparator has a first input coupled to the first gain network. The first comparator further has a second input selectively coupled to a first bitline and selectively coupled to a second bitline. A second comparator has a first input coupled to the second gain network. The second comparator further has a second input selectively coupled to the first bitline and selectively coupled to the second bitline.

Dual gain column structure for column power area efficiency

A method of counting photons using a plurality of single photon avalanche diodes (SPADs), including initiating a detection phase, enabling each single photon avalanche diode (SPAD) of the plurality of SPADs for a period of time within the detection phase, accumulating a SPAD event from each SPAD of the plurality of SPADs, wherein each SPAD event corresponds to a detection of a single photon, determining a counter code at an end of the detection phase, where the counter code corresponds to accumulated SPAD events, and enabling one or more SPADs of the plurality of SPADs within an exposure phase based on the counter code, where the counter code is greater than an expected number of the SPAD events during the exposure phase, and where the expected number of SPAD events during the exposure phase is based on the counter code that is determined at the end of the detection phase.

Low power single photon avalanche diode photon counter with peak current suppression technique

A pixel cell readout circuit comprises a comparator with a current mirror having first and second current paths, a first input transistor coupled to the first current path, a low conversion gain (LCG) second input transistor selectively coupled to the second current path, and a high conversion gain (HCG) second input transistor selectively coupled to the second current path. The pixel cell readout circuit further comprises a gain network coupled between a gate node of the first input transistor and a ramp generator output, wherein the gain network is configured to provide a variable comparator gain to the comparator, an LCG auto-zero switch coupled between a drain node and a gate node of the LCG second input transistor, and an HCG auto-zero switch coupled between a drain node and a gate node of the HCG second input transistor.

An imaging device includes a pixel array of pixel circuits arranged in rows and columns. Bitlines are coupled to the pixel circuits. Clamp circuits are coupled to the bitlines. Each of the clamp circuits includes a clamp short transistor to a power line and a respective one of the bitlines. The clamp short transistor is configured to be switched in response to a clamp short enable signal. A first diode drop device is coupled to the power line. A clamp idle transistor is coupled to the first diode drop device such that the first diode drop device and the clamp idle transistor are coupled between the power line and the respective one of the bitlines. The clamp idle transistor is configured to be switched in response to a clamp idle enable signal.

Bitline settling and power supply rejection ratio in a nine cell pixel image sensor with phase detection autofocus

An arithmetic logic unit (ALU) includes a front end latch stage coupled to a signal latch stage coupled to a Gray code (GC) to binary stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. An adder input latch stage includes first and second adder input latches including first and second inputs coupled to receive outputs of the GC to binary stage. An adder input multiplexer stage includes an output coupled to second inputs of the adder stage, and first and second inputs coupled to outputs the first and second adder input latches, respectively.

Image signal and phase detection autofocus signal extraction and storage in an arithmetic logic unit

Methods and apparatuses for a channel estimation and prediction operation in a wireless communication systems. A method of a BS comprises: receiving an SRS; partitioning, based on a partition policy, a frequency band of the SRS into sub-bandwidths in a frequency domain; generating, based on previously stored CSI in memory and the partition policy, a set of chunks corresponding to respective sub-bandwidths; performing CHPD operations corresponding to the respective sub-bandwidths to generate channel parameters, wherein different CHPD operations are applied to the respective sub-bandwidths; combining the channel parameters predicted from the respective sub-bandwidths in the frequency domain; and performing, based on the combined channel parameters, a channel estimation and prediction operation.

Method and apparatus for bandwidth-adaptive and model-order-adaptive channel prediction

An arithmetic logic unit (ALU) includes a front end latch stage coupled to a signal latch stage coupled to a Gray code (GC) to binary stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. Outputs of the adder stage are generated in response to the first inputs and second inputs of the adder stage. A pre-latch stage is coupled to latch outputs of the adder stage. A feedback latch stage is coupled to latch outputs of the pre-latch stage. The second inputs of the adder stage are coupled to receive outputs of the feedback latch stage. The feedback stage includes first conversion gain feedback latches configured to latch outputs of the pre-latch stage having a first conversion gain and second conversion gain feedback latches configured to latch outputs of the pre-latch stage having a second conversion gain.

Column arithmetic logic unit design for dual conversion gain sensor supporting correlated multiple sampling and three readout phase detection autofocus

In an embodiment, a method of reducing resistance-capacitance delay along photodiode transfer lines of an image sensor includes forking a plurality of photodiode transfer lines each into a plurality of sublines coupled together and to a first decoder-driver at a first end of each subline; and distributing selection transistors of a plurality of multiple-photodiode cells among the plurality of sublines. In embodiments, the sublines may be recombined at a second end of the sublines and driven by a second decoder-driver at the second end.

Circuit and method for image artifact reduction in high-density, high-pixel-count, image sensor with phase detection autofocus

A pressure-resistant hull for a submersible, includes unit hulls, reinforcing ribs, connecting channels, and closure heads. A plurality of unit hulls are provided, and are sequentially strung together spiralling upward or spiralling downward, the closure heads being arranged on the unit hulls at the first position and the last position respectively, an observation window being provided on each unit hull respectively, adjacent two unit hulls in a horizontal direction being respectively connected by means of a reinforcing rib, and at least two connecting channels being provided between adjacent two rings of the unit hulls in the vertical direction. The design method includes using a spiral joining structure to facilitate organic adjustment of the number of unit hulls, thus having better utilization of space and aiding to greatly expand the space. The sensitivity of the limit load to defects is low, increasing axial rigidity, improving the overall pressure-resistive ability.

Pressure-resistant hull for a submersible and design method therefor

A ramp buffer circuit includes an input device having an input coupled to receive a ramp signal. A bias current source is coupled to an output of the input device. The input device and the bias current source are coupled between a power line and ground. An assist current source is coupled between the output of the input device and ground. The assist current source is configured to conduct an assist current from the output of the input device to ground only during a ramp event generated in the ramp signal.

Ramp settling assist circuit in local ramp buffer circuit

An imaging device includes groupings of photodiodes having four photodiodes. A transfer transistor is between each photodiode and a floating diffusion. Each floating diffusion is coupled to up to two photodiodes per grouping at a time through transfer transistors. A buffer transistor is coupled to each floating diffusion. The buffer transistors may be in a first or second grouping of buffer transistors. A first bit line is coupled to up to two buffer transistors of the first grouping and a second bit line is coupled to up to two buffer transistors of the second grouping of buffer transistors at a time. A color filter array including a plurality of groupings of color filters is disposed over respective photodiodes of the photodiode array, wherein each grouping of color filters includes four color filters having a same color, wherein each grouping of color filters overlaps two groupings of photodiodes.

Image sensor with shifted color filter array pattern and bit line pairs

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San Jose, CA, United States of America

Rui Wang