Globalfoundries Singapore Pte. Ltd.

Globalfoundries U.S. Inc.

Rui Tze Toh

Shaoqiang Zhang

Guan Huei See

Purakh Raj Verma

Raj Verma Purakh

Vibhor Jain

John Joseph Pekarik

Alexander M Derrickson

Anupam Dutta

Bo Yu

Oscar Restrepo

Fangyue Liu

Mark David Jaffe

Yung Fu Chong

Shyam Parthasarathy

Vvss Satyasuresh Choppalli

Kouassi Sebastien Kouassi

V V S S Satyasuresh Choppalli

Tao Jiang

The present disclosure relates to semiconductor structures and, more particularly, to under-body source contact structures and methods of manufacture. The structure includes: a gate structure on a semiconductor layer; a drift region within the semiconductor layer, below the gate structure; a body region within the semiconductor layer, below the gate structure; a contact region within the body region, the contact region being devoid of a silicide contact; and a silicide contact remote from the contact region within the semiconductor layer.

Under-source body contact

A semiconductor device includes a first substrate, a second substrate bonded to the first substrate, and at least one thermally conductive structure that extends through a portion of the first substrate and a portion of the second substrate and is vertically aligned with an active region of the first substrate. The at least one thermally conductive structure is electrically insulated from electrically active structures in the semiconductor device. The thermally conductive structure acts as a heat sink to transfer heat from the active region.

Heat sink for face bonded semiconductor device

Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises an intrinsic base including a first semiconductor layer, a collector including a second semiconductor layer, and an emitter including a third semiconductor layer. The first semiconductor layer, which comprises silicon-germanium, includes a first portion and a second portion adjacent to the first portion. The second semiconductor layer includes a portion on the first portion of the first semiconductor layer, and the third semiconductor layer includes a portion on the second portion of the first semiconductor layer. The structure further comprises a dielectric spacer laterally between the portion of the second semiconductor layer and the portion of the third semiconductor layer.

Heterojunction bipolar transistors with terminals having a non-planar arrangement

The embodiments herein relate to contact via structures of semiconductor devices and methods of forming the same. A semiconductor device is provided. The semiconductor device includes a substrate, a conductive feature over the substrate, and a contact via structure over and electrically coupling to the conductive feature. The contact via structure has a concave profile.

Contact via structures of semiconductor devices

Integrated circuits and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes providing a substrate including a semiconductor layer over an insulator layer. The method includes selectively replacing portions of the semiconductor layer with insulator material to define an isolated semiconductor layer region. Further, the method includes selectively forming a relaxed layer on the isolated semiconductor layer region. Also, the method includes selectively forming a strained layer on the relaxed layer. The method forms a device over the strained layer.

Integrated circuits with selectively strained device regions and methods for fabricating same

Integrated circuits and methods of producing the same are provided herein. In accordance with an exemplary embodiment, an integrated circuit includes an SOI substrate with an active layer overlying a buried insulator layer that in turn overlies a handle layer. A source is defined within the active layer, and a gate well is also defined within the active layer. A first ultra shallow trench isolation extends into the active layer, where a first portion of the active layer is positioned between the first ultra shallow trench isolation and the buried insulator layer. The first ultra shallow trench isolation is positioned between the source and the gate well.

Integrated circuits with deep and ultra shallow trench isolations and methods for fabricating the same

Devices and methods for forming a device are disclosed. A substrate is provided. A first body well of a second polarity type is formed in the substrate. A second body well of the second polarity type is formed in the first body well. A bottom of the second body well and a bottom of the first body well are contiguous. Dopant concentrations of the first and second body wells include a graded profile. A transistor of a first polarity type is formed over the substrate. The transistor includes a source and a drain. The source is formed in the second body well.

Extended drain metal-oxide-semiconductor transistor

Methods of forming a SOI PA and RF switch device having a thin BOX layer in the PA power cell region and a thick metal layer directly under the thin BOX layer and the resulting device are provided. Embodiments include providing a SOI structure having a substrate, BOX, device and metallization layers; bonding a handling layer to the metallization layer; removing the substrate; forming a passivation oxide layer over the BOX; forming first and second trenches through the passivation, BOX, and device layers down to the metallization layer; forming a third trench through the passivation layer and a portion of the BOX above a PA power cell region of the SOI structure, a thin portion of the BOX remaining; forming a first backside contact in the first trench; and forming a second backside contact in the second and third trenches and over a portion of the passivation oxide layer.

Heat dissipation and series resistance reduction of PA and RF switch in SLT by backside thick metal

Integrated circuits and methods for manufacturing the same are provided. A method for producing an integrated circuit includes forming a deep isolation block in an SOI substrate, where the SOI substrate includes a substrate layer overlying a buried insulator that in turn overlies a carrier wafer. The deep isolation block extends through the substrate layer and contacts the buried insulator. A shallow isolation block is formed in the substrate layer, where the shallow isolation block overlies a portion of the substrate layer. An isolation mask is formed overlying at least a portion of the deep isolation block to form a masked isolation block and an exposed isolation block, where the exposed isolation block includes the shallow isolation block. The exposed isolation block is removed such that a trough is defined in the substrate layer where the shallow isolation block was removed, and a gate is formed within the trough.

Integrated circuits using silicon on insulator substrates and methods of manufacturing the same

Integrated circuits and methods of producing such integrated circuits are provided. In one example, an integrated circuit has a working layer that includes a semiconductor substrate. A handle layer underlies the working layer, where a gap is defined in the handle layer such that an upper gap surface underlies the working layer. The gap has a gap area measured along a first plane at the gap upper surface. A switch directly overlies the gap, where the switch has a switch area measured along a second plane parallel with the first plane. The switch area is less than the gap area.

Integrated circuits with gaps

Silicon-on-insulator integrated circuits including body contact structures and methods for fabricating the same are disclosed. A method for fabricating a silicon-on-insulator integrated circuit includes filling a plurality of first and second shallow isolation trenches with an insulating material to form plurality of first and second shallow trench isolation (STI) structures, the plurality of second shallow isolation trenches having doped regions therebeneath, and forming a gate structure over the semiconductor layer that includes a first portion disposed over and parallel to at least two of the plurality of second STI structures and a second portion disposed in between the at least two of the plurality of second STI structures. The method further includes forming contact plugs to a body contact or gate region of the semiconductor layer. The body contact region includes a portion of the semiconductor layer between at least one of the plurality of first STI structures and at least one of the plurality of second STI structures.

Silicon-on-insulator integrated circuit devices with body contact structures and methods for fabricating the same

Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate, where the substrate includes a buried oxide (BOX) layer positioned between a handle layer and a semiconductor layer. An electronic component overlies the buried oxide layer on a semiconductor layer side, and a gate line is electrically connected to the electronic component. A body line is also electrically connected to the electronic component. A first through BOX contact electrically connects the gate line with the handle layer, and a second through BOX contact electrically connects the body line with the handle layer.

Integrated circuits with contacts through a buried oxide layer and methods of producing the same

Devices and methods for forming a device are presented. The method includes providing a substrate having at least a first region and a second region prepared with isolation regions. The first region is referred to as a chip guarding area and the second region defines a chip region of which at least one transistor is to be formed. The substrate includes a top surface layer, a support substrate and an insulator layer in between them. A transistor is formed in the second region and a substrate contact structure is formed in the first region. The substrate contact structure passes through at least the top surface layer, insulator layer and isolation region and contacts a doped region in the support substrate. The substrate contact structure is connected to at least one conductive line with a desired potential to prevent charging of the support substrate at system level.

Growing community of inventors

Singapore, Singapore

Rui Tze Toh