Intel Corporation

Rui Ma

Ayan Kar

Kalyan C Kolluru

Biswajeet Guha

Brian Joseph Greene

Chung-Hsun Lin

Nicholas A Thomson

Nathan Jack

Benjamin Orr

Rishabh Mehandru

Curtis Tsai

Kevin Fischer

Frank Patrick O'Mahony

Avyaya Jayanthinarasimham

Rohit Grover

Adam Clay Faust

Lin Hu

Sabih Omar

Substrate-less silicon controlled rectifier (SCR) integrated circuit structures, and methods of fabricating substrate-less silicon controlled rectifier (SCR) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin portion and a second fin portion that meet at a junction. A plurality of gate structures is over the first fin portion and a second fin portion. A plurality of P-type epitaxial structures and N-type epitaxial structures is between corresponding adjacent ones of the plurality of gate structures. Pairs of the P-type epitaxial structures alternate with pairs of the N-type epitaxial structures.

Substrate-less silicon controlled rectifier (SCR) integrated circuit structures

Substrate-free integrated circuit structures, and methods of fabricating substrate-free integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin, a plurality of gate structures over the fin, and a plurality of alternating P-type epitaxial structures and N-type epitaxial structures between adjacent ones of the plurality of gate structures.

Substrate-free integrated circuit structures

Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices. In some embodiments, an IC structure may include: a device layer, wherein the device layer includes a plurality of active devices; a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer; a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and a conductive via in the device layer, wherein the conductive via is in conductive contact with at least one of the active devices in the device layer and also in conductive contact with the second conductive pathway.

Integrated circuit structures including backside vias

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Portland, OR, United States of America

Rui Ma