Qualcomm Incorporated

Applied Materials, Inc.

Ebay, Incorporated

Pinterest, Inc.

Rui Li

Xiangjin Xie

Xianmin Tang

Sei Seung Yoon

Venkat Narayanan

De Lu

Chulmin Jung

Fuhong Zhang

Tae Hong Ha

Bin Liang

Daniel Lawrence Stasiak

Martin Saint-Laurent

Lu Chen

Shirish A Pethe

Lanlan Zhong

Sanjay Bhagawan Patil

Martin Lee Riker

Li-chung Chang

Adolph Miller Allen

Joung Joo Lee

Feng Chen

David Anthony Kidd

Harish Venkatachari

Timothy Donald Gathman

Haitao Wang

Jurij Leskovec

Gregory Ameriada Uvieghara

Wei Zhuo

Rahul Karmaker

Paolo Minero

Anthony Chih-Tung Chan

Ming Liu

Gang Shen

Tony Chung Yiu Kwok

Yu Fu

Min Chen

Qian Ma

Suresh Raman

Antriksh Pany

Saravanan Marimuthu

Samy Shafik Tawfik Zaynoun

Noufal Kappachali

Ashwin Alur Sreesha

Srivatsan Chellappa

Peeyush Kumar Parkar

Baldeo Sharan Sharma

Dhananjay Shrouty

Emaad Ahmed Manzoor

Yida Lin

Rimal Patel

Arpit Chitransh

Masoud Azmoodeh

Amit Patil

Wenbang Xu

Martin Pierre Saint-Laurent

Li-Chung Chang

Methods and apparatus for forming a barrier layer are provided herein. In some embodiments, a method of forming a barrier layer on a substrate includes treating an exposed layer deposited on a substrate and within a feature of the substrate by pulsing a bias power applied to a substrate support supporting the substrate while exposing the layer to a plasma. The exposed layer can be deposited by an atomic layer deposition process, and can be, for example, a tantalum nitride layer. The bias power can be up to 500 watts of RF power at a pulse frequency of about 1 Hz to about 10 kHz. The bias power can be pulsed uniformly or at multiple different levels.

Pulsing plasma treatment for film densification

Systems and methods for automatically placing a taxonomy candidate within an existing taxonomy are presented. More particularly, a neural taxonomy expander (a neural network model) is trained according to the existing, curated taxonomic hierarchy. Moreover, for each node in the taxonomic hierarchy, an embedding vector is generated. A taxonomy candidate is received, where the candidate is to be placed within the existing taxonomy. An embedding vector is generated for the candidate and projected by a projection function of the neural taxonomy expander into the taxonomic hyperspace. A set of closest neighbors to the projected embedding vector of the taxonomy candidate is identified and the closest neighbor of the set is assumed as the parent for the taxonomy candidate. The taxonomy candidate is added to the existing taxonomic hierarchy as a child to the identified parent node.

Neural taxonomy expander

Methods of forming copper interconnects are described. A doped tantalum nitride layer formed on a copper layer on a substrate has a first amount of dopant. The doped tantalum nitride layer is exposed to a plasma comprising one or more of helium or neon to form a treated doped tantalum nitride layer with a decreased amount of dopant. Apparatus for performing the methods are also described.

Impurity removal in doped ALD tantalum nitride

Methods and apparatus for processing a substrate are provided herein. For example, an RF power delivery compensation circuit comprises a first input configured to receive an RF forward power from an RF power source connected to a processing chamber and a second input configured to receive an RF delivered power from a matching network connected between the RF power source and the processing chamber. The RF power delivery compensation circuit calculates an RF forward power compensation factor based on the RF forward power and the RF delivered power for adjusting the RF forward power delivered to the processing chamber during operation.

Methods and apparatus for processing a substrate

Methods, systems, and devices for wireless communications are described. A user equipment (UE) may operate in a dual-connectivity (DC) configuration, and may measure signals from more than one radio access technology (RAT). The UE may receive a first signal power for a first RAT and a second signal power for a second RAT. The UE may determine a common gain state for the first RAT and the second RAT based on the first signal power and the second signal power. The UE may then apply the common gain state to a first receiver chain within the UE for the first RAT and to a second receiver chain within the UE for the second RAT, where the first receiver chain and the second receiver chain share at least one shared low noise amplifier (LNA).

Common automatic gain control across multiple radio access technologies

Aspects of the disclosure are directed to sensing integrated circuit (IC) Back End Of Line (BEOL) process corners. In one aspect, an apparatus for sensing IC BEOL process corners includes a ring oscillator including a plurality of ring oscillator stages configured to generate an output waveform with a frequency state; and a shield net circuit including a plurality of shield net stages corresponding to the plurality of ring oscillator stages, the shield net circuit having a toggle input. And, a method includes generating an output waveform with a frequency state using a ring oscillator that includes a plurality of ring oscillator stages; modifying a plurality of ring oscillator stage time delays through a coupling between a plurality of shield net stages and the plurality of ring oscillator stages; and selecting the frequency state using a toggle input of a shield net circuit which includes the plurality of shield net stages.

Back end of line (BEOL) process corner sensing

An aspect of the disclosure relates to a latch array, including: a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a first set of data, and a first set of data outputs coupled to a set of bitlines, respectively; a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write-bit inputs configured to receive a set of write-bit signals, and a set of write-bit outputs coupled to a set of write-bit lines, respectively; and an array of slave latches, wherein the slave latches in columns of the array include a second set of data inputs coupled to the set of bitlines, and a second set of write-bit inputs coupled to the set of write-bit lines, respectively.

Latch array with mask-write functionality

A latch array including a row of master latches coupled to columns of slave latches. Each master latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch an input data, and each slave latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch the data from the master latch, and an inverter including an input coupled to the AOI gate and an output to produce an output data based on the input data. Alternatively, each master latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch an input data, and each slave latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch the data from the master latch, and an inverter including an input coupled to the OAI gate and an output to produce an output data.

True single phase clock (TSPC) based latch array

Embodiments disclosed herein generally relate to methods of depositing a plurality of layers. A doped copper seed layer is deposited in a plurality of feature definitions in a device structure. A first copper seed layer is deposited and then the first copper seed layer is doped to form a doped copper seed layer, or a doped copper seed layer is deposited directly. The doped copper seed layer leads to increased flowability, reducing poor step coverage, overhang, and voids in the copper layer.

Method of depositing multilayer stack including copper over features of a device structure

Methods and apparatus for filling features on a substrate are provided herein. In some embodiments, a method of filling features on a substrate includes: depositing a first metallic material on the substrate and within a feature disposed in the substrate in a first process chamber via a chemical vapor deposition (CVD) process at a first temperature; depositing a second metallic material on the first metallic material in a second process chamber at a second temperature and at a first bias power to form a seed layer of the second metallic material; etching the seed layer in the second process chamber at a second bias power greater than the first bias power to form an intermix layer within the feature comprising the first metallic material and the second metallic material; and heating the substrate to a third temperature greater than the second temperature, causing a reflow of the second metallic material.

Methods and apparatus for intermixing layer for enhanced metal reflow

A true random number generator (TRNG) for generating a sequence of random numbers of bits is disclosed. The TRNG includes a TRNG cell configured to generate a sequence of bits logically alternating with a mean frequency and with substantially random period jitter; a period monitor configured to generate a first sequence of random bits based on a set of periods of the sequence of logically alternating bits; and a sampling circuit configured to sample the first sequence of random bits in response to a sampling clock to generate a second sequence of random bits.

True random number generator based on period jitter

Methods and apparatus for method for filling a feature with copper. In some embodiments, the methods include: (a) depositing a first cobalt layer via a physical vapor deposition (PVD) process atop a substrate field and atop a sidewall and a bottom surface of a feature disposed in a substrate to form a first cobalt portion atop the substrate field and a second cobalt portion atop the sidewall; (b) depositing copper atop the first cobalt portion atop the substrate field; and (c) flowing the copper disposed atop the first cobalt portion atop the substrate field over the second cobalt portion and into the feature, wherein the first cobalt portion atop the substrate field reduces the mobility of copper compared to the mobility of copper over the second cobalt portion.

Methods and apparatus for filling a feature disposed in a substrate

A filter circuit may include a first path having a first complex baseband filter. The circuit may further include a second path having a second complex baseband filter. The circuit may further include a combiner coupled to an output of the first complex baseband filter and an output of the second complex baseband filter.

Filter circuit

A computer-readable storage medium for controlling voltage droop storing instructions that, when executed by a processor, cause a device to perform operations including receiving a first voltage to a first input of a first component of a device. The first voltage corresponding to a first logical value causes a first internal power supply of the first component to be charged using an external power supply. The operations further include providing a second voltage to a second input of a second component of the device in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second voltage corresponding to the first logical value causes a second internal power supply of the second component of the device to be charged using the external power supply.

Voltage droop control

Growing community of inventors

San Jose, CA, United States of America

Rui Li