International Business Machines Corporation

Huawei Technologies Co., Limited

Chengdu Boe Optoelectronics Technology Co., Ltd.

Boe Technology Group Co., Ltd.

Beijing Boe Technology Development Co., Ltd.

Rui Hou

Kun Wang

Yi Ge

Ke Zhang

Lixin Zhang

Huayong Wang

Wei Liu

Zhi Peng Liu

Yan Qi Wang

Liang Liu

Yu Zhang

Ning Zhang

Zhen Bo Zhu

Xiao Tao Chang

Yulin Wang

Hua Wang

Xiangdan Dong

Harold Wade Cain, Iii

Kun-Lung Wu

Ying Li

Liqiang Chen

Bugra Gedik

Tao Gao

Mengmeng Du

Zhen Li

Xiaowei Shen

Ye Li

Rong Wang

Henrique Andrade

Xu Liang Li

Yanxin Wang

Changlong Yuan

Xiao Zhong

Yaming Wang

Guoyi Cui

Le Chang

Jiali Wang

Wu Yu Hui

Chuntong Jiang

Yao Zou

Qiong Zou

Hong Bo Zeng

Yinbo Xian

Yide Du

Shasha Zhu

Xubin Guo

Yujing Feng

Dongfeng Su

Liuhang Zhang

A display substrate and a display device. A sub-pixel in the display substrate comprises: a first initialization signal line and a second initialization signal line, the potentials of initialization signals transmitted by the first initialization signal line and the second initialization signal line being different; a sub-pixel driving circuit in the sub-pixel comprises a drive transistor, a first reset transistor and a second reset transistor; a first electrode of the drive transistor is coupled to a light-emitting element; a first electrode of the first reset transistor is coupled to a gate electrode of the drive transistor, and a second electrode of the first reset transistor is coupled to the first initialization signal line; a first electrode of the second reset transistor is coupled to the light-emitting element, and a second electrode of the second reset transistor is coupled to the second initialization signal line.

Display substrate and display device having compensation signal lines coupled to initialization signal lines

A flexible display screen includes: a flexible substrate (); an OLED device layer () formed on the flexible substrate (); an encapsulation layer(), disposed on the OLED device layer() and encapsulating the OLED device layer (); and an encapsulation protection layer () formed on the encapsulation layer (). The embodiments of the present disclosure also provide a flexible display device and a manufacturing method of the flexible display screen.

Flexible display screen including encapsulation protection layer, flexible display device, and manufacturing method thereof

This disclosure provides a packaging structure for a display substrate, a packaging method and a display device. The packaging structure for the display substrate includes a base substrate, a light-emitting device arranged on the base substrate, and a packaging thin film covering the light-emitting device. The packaging thin film includes an inorganic thin film and an organic thin film that are laminated, and the organic thin film is arranged on a surface of the inorganic thin film away from the base substrate. The packaging thin film includes a central region and a peripheral region surrounding the central region, the inorganic thin film located in the central region has surface energy greater than that of the inorganic thin film in the peripheral region, and the organic thin film in the central region has a thickness less than that of the organic thin film in the peripheral region.

Packaging structure for display substrate, packaging method and display device

A display panel, a method for manufacturing the same and a display device are provided. The display panel includes a substrate and a packaging layer. An edge of a first side of the packaging layer has a first slope. Touch lines are disposed on a side of the packaging layer away from the substrate, an extending direction of at least a portion of the touch lines is crossed with an extending direction of the edge of the packaging layer with the first slope. The touch lines include first lines, second lines and a first insulating layer. The second lines are electrically coupled to the first lines through vias in the first insulating layer. An orthographic projection of at least a portion of the first lines on the substrate is not overlapped with an orthographic projection of a portion of the packaging layer with the first slope on the substrate.

Display panel and method for manufacturing the same, display device

A memory management method implemented by a requesting node includes sending first indication information used for indicating a length of memory required by the requesting node and receiving second indication information used for indicating first remote memory provided to the requesting node by a target contributing node in at least one contributing node that can provide remote memory. The method also includes determining, from available virtual addresses, a first virtual address corresponding to the first remote memory, and sending a first data read/write instruction for the first data when first data whose pointer is within a range of the first virtual address needs to be read/written, where the first data read/write instruction includes third indication information, and the third indication information is used for indicating storage space, for storing the first data, in the first remote memory.

Memory management method, apparatus, and system

A method and an apparatus for querying a physical memory address where the method includes storing, into a prefetch buffer, page table entries of a second thread that is to perform addressing that are stored in a standby buffer, where the standby buffer stores page table entries that are not queried within a set time in a translation lookaside buffer (TLB), receiving a memory addressing request message that carries a virtual address and is sent by the second thread, and querying, in the TLB and the prefetch buffer, a corresponding physical address according to the virtual address.

Method and apparatus for querying physical memory address

Provided is a hardware accelerator and method, central processing unit, and computing device. A hardware accelerating method includes, in response to a request for a new task issued by a hardware thread, accelerating processing of the new task and producing a processing result for the task. A predicting step predicts total waiting time of the new task for returning to a specified address associated with the hardware thread.

Hardware acceleration wait time awareness in central processing units with multi-thread architectures

Provided is a hardware accelerator, central processing unit, and computing device. A hardware accelerator includes a task accelerating unit configured to, in response to a request for a new task issued by a hardware thread, accelerate the processing of the new task and produce a processing result for the task; a task time prediction unit configured to predict the total waiting time of the new task for returning to a specified address associated with the hardware thread. One aspect of this disclosure makes the hardware thread aware of the time to be waited for before getting a processing result, facilitating its task planning accordingly.

A multilevel cache-based data read/write method and a computer system. The method includes acquiring a query address of a physical memory data block in which data is to be read/written, acquiring a cache location attribute of the physical memory data block, querying whether a cache is hit until one cache is hit or all caches are missed, where the querying is performed according to the query address in descending order of levels of caches storable for the physical memory data block, and the levels of the caches are indicated by the cache location attribute, and if one cache is hit, reading/writing the data in the query address of the physical memory data block in the hit cache; or, if all caches are missed, reading/writing the data in the query address of the physical memory data block in a memory.

Multilevel cache-based data read/write method and apparatus, and computer system

A cross-page prefetching method, apparatus, and system are disclosed, which can improve a prefetching hit ratio of a prefetching device, and further improve efficiency of memory access. The method includes: receiving an indication message, sent by a cache, that a physical address is missing, where the indication message carries a mapped-to first physical address and contiguity information of a first physical page to which the first physical address belongs; acquiring a prefetching address according to the first physical address and a step size that is stored in a prefetching device; and if a page number of a physical page to which the prefetching address belongs is different from a page number of the first physical page, and it is determined, according to the contiguity information of the first physical page, that the first physical page is contiguous, prefetching data at the prefetching address.

Cross-page prefetching method, apparatus, and system

Apparatus and methods are provided for controlling the loading status of DLLs. Specifically, a streaming program compiler is provided. The compiler includes operation modules for calling DLLs during streaming program execution; association table generating units for generating association tables according to user-defined rules, where the association table includes entries indicating (i) stream branches of the streaming program and (ii) an operation module corresponding to the stream branches; and a trigger generating unit for generating a trigger based on user-defined rules, where the trigger generating unit (i) determines which conditions for loading and unloading DLLs fit the streaming program, (ii) matches these conditions to a particular stream branch to identify a matched stream branch, and (iii) sends out triggering signals indicating the matched stream branch. This invention also provides a corresponding method and controller.

Method and system for loading status control of DLL

The present disclosure provides a method, device, and system for processing a request in a multi-core system. The method comprises steps of: receiving a request for data by a filter from a requesting unit; comparing an indicator indicative of a logical partition in the request with an indicator indicative of the logical partition in a record of the filter; searching in a unit where the filter is located based on the request and returning a search result to the requesting unit if a comparison result matches; and returning a NONE response to the requesting unit from the filter if the comparison result does not match.

Data processing, method, device, and system for processing requests in a multi-core system

One embodiment of a method for constructing executable code for a component-based application includes receiving a request to compile source code for the component-based application, wherein the request identifies the source code, and wherein the source code comprises a plurality of source code components, each of the source code components implementing a different component of the application, and performing a series of steps for each source code component where the series of steps includes: deriving a signature for the source code component, retrieving a stored signature corresponding to a currently available instance of executable code for the source code component, comparing the derived signature with the stored signature, compiling the source code component into the executable code when the derived signature does not match the stored signature, and obtaining the executable code for the source code component from a repository when the derived signature matches the stored signature.

Incrementally constructing executable code for component-based applications

A processing unit coupled to a bus for accelerating data transmission and a method for accelerating data transmission. The present invention provides a streaming data transmission mode in which a plurality of data blocks are transmitted via one handshake. The present invention employs handshake save policy, when a processing unit sends a request comprising a plurality of data blocks on a bus, a cache or memory will perform address matching to judge whether there is any hit data block. If there is any hit data block, the cache or memory only needs to reply once and then start to continuously transmit the hit data blocks it possesses. Thus, a separate handshake for each data block is no longer needed.

Processing unit, chip, computing device and method for accelerating data transmission

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Beijing, China

Rui Hou