Lsi Logic Corporation

Lsi Corporation

Ruggero Castagnetti

Ramnath Venkatraman

Subramanian Ramesh

Yauh-Ching Liu

Gary K Giust

Franklin Duan

Arvind Kamath

Helmut Puchner

Benjamin Mbouombouo

Prabhakar Pati Tripathi

Weiran Kong

Steven Michael Peterson

Joseph Eugene Glenn

Shiva Ramesh

Shih-Fen Huang

Myron J Buer

Minh Tien Nguyen

Shashidhara S Bapat

Ramnath Ventatraman

Lee Phan

A rush-in current controller includes a clock module connected to provide a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal. Additionally, the rush-in current controller includes a ring oscillator module connected to maintain the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage. A method of controlling a rush-in current includes providing a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal and maintaining the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage.

Power controller for SoC power gating applications

A method of reducing total power dissipation for logic cells includes selecting a distribution of logic cells corresponding to at least one path, computing a dynamic to static power ratio for each logic cell in the distribution of logic cells and ranking the dynamic to static power ratio for each logic cell into a lower group, a middle group and an upper group of logic cells. Additionally, the method includes swapping the lower group of logic cells and the upper group of logic cells for a reconfigured middle group of logic cells and verifying path timing for the reconfigured middle group of logic cells. Methods of reducing total power dissipation using Boolean equations and for logic cell sets are also provided.

Total power optimization for a logic integrated circuit

An integrated circuit power supply decoupling circuit includes a capacitor and a protection circuit. The capacitor has a first terminal and a second terminal. The protection circuit includes a first transistor having a first conduction path, and a second transistor having a second conduction path. One terminal of the first conduction path is connected to the first terminal of the capacitor, and another terminal of the first conduction path is connected to a first power supply rail. One terminal of the second conduction path is connected to the second terminal of the capacitor, and another terminal of the second conduction path is connected to a second power supply rail.

Defectivity-immune technique of implementing MIM-based decoupling capacitors

A method incorporating adaptive body biasing into an integrated circuit design flow includes the steps of (A) adding adaptive body biasing input/outputs (I/Os) during a bonding layout stage of the integrated circuit design flow, (B) floorplanning the integrated circuit design, (C) generating an adaptive body biasing mesh and (D) generating a layout of the integrated circuit design based upon a plurality of adaptive body biasing corners.

Optimization with adaptive body biasing

Disclosed is a method and device for providing fast-response One-Time-Programmable (OTP) memory based on SRAM memory technology and the inherent breakdown characteristics of a MOS transistor. Each memory cell of an SRAM memory cell circuit is connected to a programming circuit. The programming circuit is comprised of two groups of MOS transistors connected to the storage nodes (SN and SNB, where SNB is the complementary value of SN) of the two cross-coupled inverters of the SRAM memory circuit. A desired data set is loaded into the circuit and then is burned-in by applying and repeatedly cycling a 'burn-in' voltage across the source and drain of the MOS transistors of the programming circuit that approaches the ON STATE trigger voltage of the characteristic bipolar junction transistor contained within the MOS transistors. Upon repeated cycling of the source-to-drain voltage, the targeted MOS transistor within the programming circuit breaks down and shorts across the gate, drain, and/or source of the transistor. When the system is returned to normal operation, the programming circuits will be connected to ground, Vdd or Vss and one of the two nodes of the SRAM cell circuit will be shorted through the programming circuit to ground, Vdd or Vss, thus, forcing a retention of the programmed data state.

SRAM based one-time-programmable memory

The present invention provides a system and method for designing and modularly expanding multiport bitcells. A modular design approach is described that reduces the complexity of designing multiport bitcells while complying with DFM rules across various semiconductor fabrication providers. The modular design may be parsed into modules such as read port modules, write port modules, and pull-up modules that may be easily interconnected to build a multiport bitcell. These modules may also be independently sized and assembled to achieve desired read margins, write margins, static noise margins as well as read access times and write times.

Modular design of multiport memory bitcells

Improved layouts of binary and ternary content addressable memory cells (BCAM and TCAM) are shown. A content addressable memory cell layout has a plurality of P+ diffusion areas and a plurality of N+ diffusion areas that do not enclose isolation regions and on which shallow trench isolation stress can exert minimal influence on the drive current of the memories. Further, all transistors in the content addressable memory cell layout are oriented in the same direction to avoid unintended variations in electrical performance. The CAM layouts are 'process friendly' to accommodate requirements of advanced process technologies such as the 90 nm process.

Compact ternary and binary CAM bitcell architecture with no enclosed diffusion areas

A circuit for measuring the performance of a memory cell. The circuit includes a ring oscillator, which includes a plurality of memory cells. The performance of the memory cell can be determined from an oscillation frequency of the ring oscillator. The circuit accurately verifies the performance of the memory cell without modifying the memory cell. This avoids altering the transient AC characteristics of the memory cell when predicting its performance.

Circuit for verifying the write speed of SRAM cells

Two new ternary CAM bitcell design options are presented that provide compact layout solutions while maximizing matchline channels routing through the cells. In both layouts, the first inventive layout, an asymmetric layout of the 6T-SRAM bitcell is used to improve ease of layout, density, and performance of ternary CAM cells. In the second inventive layout, n-type diffusions for the SRAM bitcell and the comparison circuit are separated, creating a bitcell having a more even cell aspect ratio.

Ternary CAM bitcells

A memory cell architecture is provided herein for increasing memory speed, performance and robustness within a highly compact memory cell layout. Though only a few embodiments are provided herein, a feature common to all embodiments includes a novel means for sharing one or more contact structures between vertically adjacent memory cells. In particular, one or more contact structures may be shared unequally between two vertically adjacent memory cells for reducing a vertical dimension, or length, of the memory cell. Other features are disclosed for producing the highly compact memory cell layout. The various features of the present invention may be combined to produce high-performance, high-density memory arrays.

Memory cell architecture

An improved memory cell architecture is provided herein for reducing, or altogether eliminating, chip-level routing congestion in System-on-Chip environments. Though only a few embodiments are provided herein, features common to the described embodiments include: the formation of bitlines in a lower-level metallization layer of the memory array, and the use of word lines and ground supply lines, both formed in inter-level metallization layer(s) of the memory array, for effective shielding of the bitlines against routing signals in the chip-level routing layer.

Memory cell architecture for reduced routing congestion

Test structures are provided for accurately quantifying shared contact resistance. The test structures are built based upon an actual memory cell, which is self-aligning to allow shared contact chains through an array of test cells. A main array of test cells is built to provide a chain of shared contact resistance. Using the main array of test cells, a resistance in the shared contact chain may be measured. Supplemental arrays of test cells is built to provide a chain of poly side resistance, a chain of island side resistance, a chain of island connection line resistance, and a chain of poly connection resistance. A tester measures resistance using the test structures and uses the values to accurately determine shared contact resistance.

Method and apparatus for characterizing shared contacts in high-density SRAM cell design

A self-aligning memory cell design is provided to allow testing of transistors in every cell of a memory circuit. A test array of these cells is fabricated with contact pads in each cell for specific components in the cell. Then, metal lines are provided to couple the contact pads in the test array. The whole test array is then probed via these metal lines. Tests may then be performed to detect random and systematic transistor degradation electrically for all cells in the circuit. Different components in the memory design may be tested by providing contact pads for the components of interest and providing metal lines coupling the contact pads.

Method and architecture for detecting random and systematic transistor degradation for transistor reliability evaluation in high-density memory

A method and system for reconfiguring a memory array is disclosed. Initially, the cells in the memory array are patterned with substantially the same structure up to a predefined layer. Thereafter, the memory array is reconfigured by patterning the cells above the predefined layer such that a first plurality of cells function as memory cells, and a second plurality of cells are patterned as a dummy row or column that function as a breakpoint for the memory array.

Reconfigurable memory arrays

The present invention provides a method of forming a semiconductor device fuse and a semiconductor device fuse structure. A first dielectric layer is formed on top of a metal layer in a semiconductor device. The dielectric layer is patterned to provide access to at least two contacts in the metal layer. A conductive metal layer is deposited and patterned to form a fuse between the fuse contacts. A second dielectric layer is deposited on the conductive metal layer.

Growing community of inventors

Menlo Park, CA, United States of America

Ruggero Castagnetti