Industrial Technology Research Institute

Ruey-Liang Ma

Kun-Cheng Wu

Shi-Sheng Shang

Chia-Chang Hsu

Dze-chaung Wang

Yuan-Heng Sun

Jen-Yu Yu

Kang-Feng Lee

Oscal T-c Chen

Chien-kuo Tien

Chien-Kuo Tien

Yuan-Ann Chang

Shih-Wei Peng

Kuo-Hua Chen

Meng-Ru Lin

Oscal T -c Chen

I-Ping Hsu

George Shiang-Jyh Lai

A multi-diameter clamp for clamping on tires of different sizes is provided. The multi-diameter clamp comprises at least one clamping unit, at least one actuator, and at least one sensing unit. The at least one clamping unit further includes at least one movable member and a fixed member. Wherein the at least one movable member moves within a tire housing space having a starting position and a clamping position. The tire housing space locates between the movable member and the fixed member for clamping on a tire. The at least one actuator connects to the at least one movable member, and enables the at least one moveable member to move between the starting position and the clamping position. The at least a sensing unit obtains a diameter size of the tire, and based on the diameter size, actuates the at least one actuator corresponding to the diameter size.

Multi-diameter clamp for clamping on tires of different sizes

The present invention provides a non-copy shared stack and register set device and a dual language processor structure using the same, which achieve non-copy data sharing by controlling a selector and the stack pointer of a data stack. The selector is connected to each item of the data stack and a register of the register set, such that, when the register set requires to exchange data with the data stack, the selector is controlled and the stack pointer is updated thereby the selector is switched to make the stack item pointed by the stack pointer communicate with the register.

Non-copy shared stack and register file device and dual language processor structure using the same

An energy saving multiplication device and its method is disclosed. The multiplication device includes a dynamic range determination unit, a Booth encoding/decoding unit and a counter array. The dynamic range determination unit determines dynamic ranges of the numerical values to be multiplied together and outputs after processing according to the dynamic-range size relation of the input data. The Booth encoding/decoding unit couples to the dynamic range determination unit. The counter array couples to the Booth encoding/decoding unit for accumulating the partial products to obtain the products of the input data.

Energy saving multiplication device and method

An arithmetic device with low power consumption includes master latches, a dynamic range detection unit, slave latches, an operation unit, and a word-length restoration unit. In the arithmetic device, the master latches latch a plurality of (such as two) input data. The dynamic range detection unit detects the effective dynamic range of these input data. The slave latches latch the values of the effective dynamic-range bits of these input data. The operation unit performs predetermined operations of the bits of these effective dynamic range to obtaing an operation result. Since the operation unit only performs operations of the bits of the effective dynamic range, the circuit corresponding to other bits will not demonstrate switching of power consumption, thereby lowering the overall power consumption. Furthermore, the word-length restoration unit will complement the operation result to its original output length in association with the sign of the operation result, for obtaining the correct operation result.

Arithmetic device and method with low power consumption

A processor is provided with a decoder, a memory connected to the decoder and an execution stage connected to the decoder. The decoder receives each instruction. Each time the decoder receives an instruction, if the instruction contains a symbolic reference, the decoder determines whether or not the symbolic reference has been resolved into a numeric operand. If the symbolic reference has been resolved into a numeric operand, the memory retrieves, from a numeric reference table, a numeric operand to which the symbolic reference has been resolved. The execution stage then executes the instruction on the retrieved numeric operand in place of the symbolic reference. If the symbolic reference has not been resolved into a numeric operand, then the execution stage searches a data object, which relates each symbolic reference to a memory slot in which a corresponding numeric operand is stored, for a numeric reference relating the symbolic reference to a corresponding numeric operand. The memory then retrieves the numeric operand, that corresponds to the unresolved symbolic reference, from the memory slot indicated by the numeric reference of the data object. The memory stores the retrieved numeric operand in the numeric reference table maintained therein. The execution stage executes the instruction on the retrieved numeric operand in place of the symbolic reference of the instruction and indicates to the decoder that the symbolic reference is resolved. &ldquo;Resolved indications,&rdquo; which each indicates whether or not a specific, respective symbolic reference is resolved, can be stored in a numeric reference buffer and accessed using the instruction fetch address as an index. The numeric reference table can also be stored in the numeric reference buffer and accessed (indexed) the same way.

Intermediate instruction execution processor which resolves symbolic references without modifying intermediate instruction code

A processor architecture is disclosed including a fetcher, packet unit and branch target buffer. The branch target buffer is provided with a tag RAM that is organized in a set associative fashion. In response to receiving a search address, multiple sets in the tag RAM are simultaneously searched for a branch instruction that is predicted to be taken. The packet unit has a queue into which fetched cache blocks are stored containing instructions. Sequentially fetched cache blocks are stored in adjacent locations of the queue. The queue entries also have indicators that indicate whether or not a starting or final data word of an instruction sequence is contained in the queue entry and if so, an offset indicating the particular starting or final data word. In response, the packet unit concatenates data words of an instruction sequence into contiguous blocks. The fetcher generates a fetch address for fetching a cache block from the instruction cache containing instructions to be executed. The fetcher also generates a search address for output to the branch target buffer. In response to the branch target buffer detecting a taken branch that crosses multiple cache blocks, the fetch address is increased so that it points to the next cache block to be fetched but the search address is maintained the same.

System for packing variable length instructions into fixed length blocks

A stack management unit for a processing system that manages multiple stacks and corresponding stack pointer data as a frame stack. The stack management unit utilizes a combination of a primary stack and a secondary stack as the frame stack. A background spill/fill detect unit determines when an overflow/underflow of the primary stack occurs. In response to an overflow/underflow condition, the background spill/fill detect unit controls the transfer of a frame portion between the primary stack and the secondary stack without halting the processing system.

Intelligent multiple stack management unit

Methods and systems are disclosed for exploring instruction-level parallelism in superscalar processors by renaming stack entries. In a first embodiment, the stack renaming is implemented in a parallel structure that renames the instructions in parallel. In a second embodiment, the stack renaming is implemented in a serial structure that renames the instructions serially. In a third embodiment, the stack renaming is implemented in a combined parallel-serial structure that renames the instruction partially in parallel and partially in series.

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Kaohsiung, Taiwan

Ruey-Liang Ma