Taiwan Semiconductor Manufacturing Comp. Ltd.

Ruey-Bin Sheen

Chih-Hsien Chang

Tsung-Hsien Tsai

Cheng-Hsiang Hsieh

Ya-Tin Chang

Mao-Hsuan Chou

Tien-Chien Huang

Ming Hsien Tsai

Ying-Yu Hsu

Chao Chieh Li

Chen-Ting Ko

Ting-Kuei Kuan

Chuan-Yao Tan

Chung-Hui Chen

Mao-Ruei Li

Chih-hsien Chang

Yung-Chow Peng

Chao-Chieh Li

Shih-Hung Lan

Jason Hsu

Jui-Cheng Huang

Tung-Tsun Chen

Wei Chih Chen

Shyh-An Chi

Tsung-Hsin Yu

Chung-Peng Hsieh

Chin-Ming Fu

Po-Zeng Kang

Wan-Te Chen

Chien-Chun Tsai

Tzu Ching Chang

Weichih Chen

Chen-Hsiang Hsieh

Chin-Yang Wu

The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes defining a layout unit for a circuit implementation and arranging multiple layout units into a layout cell. The method also includes editing the layout cell to connect a first set of the layout units to be representative of the circuit implementation and to connect a second set of the layout units to be representative of a non-functional circuit. Further, the method includes inserting one or more dummy fill structures in areas of the layout cell unoccupied by the first and second sets of layout units.

Optimized layout cell

An automatic gain adjustor for a hybrid oscillator can be employed to overcome the frequency limitations of hybrid phase lock loops (PLLs). For example, an automatic gain adjustor for a hybrid oscillator can include a hybrid oscillator that is configured to receive a coarse tuning signal and a gain adjustment signal and generate an output signal with any frequency within the specified frequency range of the hybrid PLL. The automatic gain adjustor for a hybrid PLL may further include a fine tuning array that receives one or more fine tuning selection signals and generates a gain adjustment signal that is received by the hybrid oscillator. The fine tuning array generates a gain adjustment signal to adjust the gain of the hybrid oscillator according to an operating frequency range of the hybrid oscillator.

Automatic hybrid oscillator gain adjustor circuit

A tuning array selection circuit, together with a decoder and a voltage controlled oscillator (VCO), can be employed to overcome some disadvantages of previous methods of phase locked loops. For example, a VCO can include a coarse tuning array and a fine tuning array. A coarse tuning array can be used to tune a VCO to generate a signal within a wide frequency range. A fine tuning array can be used to tune a VCO to generate a signal within a narrow frequency range. In one embodiment, the narrow frequency range is within the wide frequency range. The tuning array selection circuit can coordinate selection of appropriate fine tuning devices and narrow tuning devices to reduce transition jitter and the risk of fail locking of phase locked loops.

Coarse-mover with sequential finer tuning step

A method of manufacturing a semiconductor device based on a dual-architecture-compatible design includes: forming transistor components of in a transistor (TR) layer; and performing one of fabricating additional components according to (A) a buried power rail (BPR) type of architecture or (B) a non-buried power rail (non-BPR) type of architecture. The step (A) includes, in corresponding sub-TR layers, forming various non-dummy sub-TR structures, and, in corresponding supra-TR layers, forming various dummy supra-TR structures which are corresponding first artifacts. The step (B) includes, in corresponding supra-TR layers, forming various non-dummy supra-TR structures and forming various dummy supra-TR structures which are corresponding second artifacts, the first and second artifacts resulting from the dual-architecture-compatible design being suitable to adaptation into the BPR type of architecture.

Method of fabricating semiconductor devices having different architectures and semiconductor devices fabricated thereby

A semiconductor structure including first finfet cells and second finfet cells. Each of the first finfet cells has an analog fin boundary according to analog circuit design rules, and each of the second finfet cells has a digital fin boundary according to digital circuit design rules. The semiconductor structure further includes first circuits formed with the first finfet cells, second circuits formed with the second finfet cells, and third circuits formed with one or more of the first finfet cells and one or more of the second finfet cells.

Circuits designed and manufactured with first and second fin boundaries

An IC structure includes a resistor circuit and a transistor. The resistor circuit includes a first metal resistor strip over a semiconductor substrate, and a first metal line and a second metal line extending on a same level height above the first metal resistor strip. The first metal resistor strip is a dummy gate. Both the first metal line and the second metal line overlap and are electrically connected to the first metal resistor strip. The transistor includes a metal gate strip on a same level height as the first metal strip and extends in parallel with the first metal resistor strip.

Integrated circuit with feol resistor

A sensing circuit coupled to a sensor includes a first transistor, a second transistor, a third transistor, a fourth transistor, and an oscillator. The first transistor, coupled to a first current source and the sensor, receives a sensing current from the sensor. A gate terminal of the first transistor is connected to a source terminal of the first transistor. The second transistor, coupled to the first transistor and a second current source, generates a first current according to the sensing current. The first current is greater than the sensing current. The third transistor, coupled to the second transistor and the second current source, generates a second current according to the first current. The fourth transistor, coupled to the third transistor, generates a third current. The oscillator is coupled to the fourth transistor. The oscillator generates a signal having an oscillation frequency according to the third current.

Sensing circuit and sensing method thereof

Systems and methods are provided for a phase locked loop. A phase/frequency detector is configured to receive a reference signal and a feedback signal. A charge pump is configured to receive outputs from the phase/frequency detector and to generate pulses. An oscillator is configured to generate an output waveform based on the charge pump pulses. A realignment path is configured to generate a clock realignment signal that is provided to the oscillator based on the outputs from the phase/frequency detector.

Systems and methods for phase locked loop realignment with skew cancellation

Systems, devices, and methods are described herein for aligning a phase of a ring oscillator and removing jitter. An oscillator includes a resistor bank array, an operational amplifier, a first and second transistor, and a realignment circuit. The resistor bank array has a plurality of resistors configured to generate a first signal. The operational amplifier is coupled to a PLL circuit and is configured to compare a voltage of the PLL circuit with a voltage of the resistor bank array. The first transistor is coupled between the operational amplifier and a ring oscillator. The first transistor is configured to generate a second signal to control a frequency of the ring oscillator during a realignment state. The realignment circuit is coupled to the first transistor and the ring oscillator. The realignment circuit is configured to generate a realignment signal to align the ring oscillator with a first clock signal.

Programmable regulator voltage controlled ring oscillator

The present disclosure provides a system of measuring capacitance of a device-under-test (DUT). The system includes first switch, second switch, and a capacitance measurement device. The first switch is configured to receive a supply voltage. The first and second switches are electrically connected to the DUT. The capacitance measurement device is configured to provide a first pair of non-overlapping periodic signals with a first frequency, and a second pair of non-overlapping periodic signals with a second frequency. The second frequency is β times the first frequency. When the first switch and the second switch receive the first pair of non-overlapping periodic signals, a first current is transmitted through the first switch and the second switch. When the first switch and the second switch receive the second pair of non-overlapping periodic signals, a second current is transmitted through the first switch and the second switch.

System and method of measuring capacitance of device-under-test

An electrical system is provided. The electrical system comprises a first phase lock circuit embedded within a first chip for receiving a first periodic signal having a first frequency. The electrical system comprises a first buffering circuit embedded within the first chip for receiving a second periodic signal having the first frequency, wherein the first buffering circuit is configured to provide a third periodic signal having the first frequency to an output terminal of the first chip.

System for signal propagation and method of operating the same

A method includes forming a shallow trench isolation (STI) region in a semiconductor substrate thereby defining an active region and a passive region in the semiconductor substrate and spaced apart from each other by the STI region, forming a first sacrificial gate structure over the active region and a second sacrificial gate structure over the passive region, forming first source/drain regions in the active region and second source/drain regions in the passive region, after forming the first and second source/drain regions, replacing the first sacrificial gate structure with a metal gate structure and the second sacrificial gate structure with a metal resistor structure, the metal resistor structure corresponding to a dummy gate, forming a first gate contact over the metal gate structure, and a pair of resistor contacts over the metal resistor structure, and electrically coupling a set of metal lines with the metal resistor structure by the pair of resistor contacts.

Integrated circuit with FEOL resistor

A device includes a phase detector circuit, a charge pump circuit, a sample and hold circuit, a comparator, and a controller. The phase detector circuit detects a clock skew between a reference signal and an input signal. The charge pump circuit translates the clock skew into a voltage. A sample and hold circuit samples the voltage, at a first time, and maintain the sampled voltage until a second time. The comparator (i) detects a loop gain associated with the input signal based on the sampled voltage and the voltage at the second time and (ii) outputs a loop gain signal for adjustment of the input signal. The controller is coupled to the phase detector, the comparator, and the sample and hold circuit. The controller generates a plurality of control signals for automatically controlling operation of the phase detector, the comparator, and the sample and hold circuit.

Loop gain auto calibration using loop gain detector

A circuit includes a period calculator and a pulse width calculator. The period calculator is configured for receiving a first predetermined digital code and a second predetermined digital code, and for calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code. The first predetermined digital code has a first predetermined period value, and the second predetermined digital code has a second predetermined period value. The pulse width calculator is configured for receiving a predetermined pulse width, and calculating a first pulse width code corresponding to the predetermined pulse width according to the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and the predetermined pulse width.

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Taichung, Taiwan

Ruey-Bin Sheen