Via Technologies, Inc.

Ruei-Ling Lin

Jiin Lai

Hung-Yi Kuo

Cheng-Wei Huang

Jui-Ming Wei

Yao-Chun Su

Sheng-Chung Wu

Hsiu-Ming Chu

Kuang-Jui Ho

Win Sheng-Cheng

Included are systems and methods for reducing power consumption in a computer system. At least one embodiment of a method, among others, includes processing data in a normal mode, receiving an indication of a transition into an idle mode, capturing at least one frame of display data, and transmitting the captured frame of display data for display during idle mode.

Reducing power during idle state

A data transmission coordinating method is used between a central processing unit and a bridge chip of a computer system. By entering the computer system into a coordinating state, the data transmission coordinating method is executed. The bridge chip and the CPU are informed of maximum bit numbers of each other for data transmission therebetween via the front side bus. Then, a commonly operable maximum bit number for data transmission between the CPU and the bridge chip can be coordinated according to the first and second maximum bit numbers. Once the commonly operable maximum bit number is determined, the CPU is reset to operate with the commonly operable maximum bit number. The maximum bit numbers are those of bus transmission width or bus transmission speed.

Data transmission coordinating method and system

In a data transmission coordinating method, the computer system enters a coordinating state, and a first signal is issued from the central processing unit to the data transmission standard storage unit of the bridge chip. In response to the first signal, a second signal is issued from the data transmission standard storage unit of the bridge chip to the central processing unit to inform the central processing unit of a first operable transmission standard of the bridge chip. After the computer system exits the coordinating state, data transmission between the central processing unit and the bridge chip is performed according to the first operable transmission standard in a first condition.

Data transmission coordinating method

A power state management method of north bridge. The north bridge monitors power transition state of processor; then adjusting operating clocks and operating voltage of the processor and the main memory according to the determined power state to saving power consumption.

Power management method of north bridge

A core logic coupled to a main memory of a computer, comprising an analyzer and a power management unit. The analyzer monitors access request traffic load of main memory. The power management unit employs various power performance trade-off activities with the knowledge of the monitored traffic load according to the state machine.

Power management system with a bridge logic having analyzers for monitoring data quantity to modify operating clock and voltage of the processor and main memory

A frequency working between the north bridge chip and random access memory of a computer system is dynamically and automatically adjusted in response to the frequency change of the CPU, in response to the workload of the north bridge chip or in response to the change of settings in a software program. The computer system may need to perform POST (Power-On Self Test) of BIOS to detect and calibrate the adjusted frequency.

Method for adjusting a frequency working between a north bridge chip and a random access memory of a computer system

A method for a power management of a central processor unit is disclosed. The method is applied to when the central processor unit is in a low power state without snooping and a bus master signal is sent from a peripheral device. First, a South Bridge sends a control signal to a central processor unit to drive the central processor unit to enter a low power state allowing snooping. Afterward an arbiter of the North Bridge is enabled. If the bus master signal is sent from the peripheral device to the South Bridge, an arbiter of the South Bridge is also enabled. And then the bus master signal is snooped by the central processor unit and the data is transmitted. After the bus master signal is snooped and the data has been transmitted, the arbiters are disabled and the South Bridge drives the central processor unit to return to the low power state without snooping.

Method for power management of central processor unit

A connected indicator wire of open-drained configuration is set between a north bridge and a south bridge. When either the south or north bridge is handling a bus master request, a bus master indicator (BMI) signal is asserted to the connected indicator wire. With open-drained configuration, the signal of the connected indicator wire is capable of reflecting whether a BMI signal is asserted, and accordingly, the south bridge controls the CPU to switch between power saving states for responding to the bus master request. The CPU does not have to resume a full-function power state to coordinate a bus master service.

Apparatus and related method of coordinating north bridge and south bridge for processing bus master requests of peripheral devices for controlling a central processing unit to operate in a power-saving state

A method for blocking a request to a front side bus interconnected between a central processing unit (CPU) and a control chip includes the following steps. First, a bus ownership of the control chip is assigned via a bus priority signal line. Any request from the CPU to the front side bus is blocked when the control chip owns the bus ownership. Meanwhile, any request from the control chip to the front side bus is inhibited when the CPU is blocked from outputting any request to the front side bus.

Growing community of inventors

Taipei, Taiwan

Ruei-Ling Lin