Siemens Aktiengesellschaft

Ruediger Mueller

Ludwig Leipold

Michael Pomper

Heiner Herbst

Karl Goser

An optoelectronic coupling element having a light-emitting semiconductor device serving as transmitter chip, and a light-receiving semiconductor device serving as a receiver chip, and are firmly connected together through an optic coupling medium (3). This compact coupling element is to have a defined degree of coupling largely independent of the housing and is to be suitable for simple conductor tape mounting. To this end, the coupling medium (3) is an insulating transparent intermediate layer, and the light-emitting semiconductor device (1), the coupling element (3) and the light-receiving semiconductor device (2) are directly laminated one on the other. This optoelectronic coupler is used in particular as an optocoupler for signal transmission.

Optoelectronic coupling element, and method of making same

A time base circuit feeds a frequency divider via a current amplifier. A current supply circuit is connected to supply the current amplifier and the frequency divider. The current supply may also be connected to supply the time base circuit; otherwise the time base circuit is responsive to electromagnetic radiation for supplying its own current.

Monolithically integrated circuit for the production of long pulses

A system is disclosed for coupling electrically isolated circuits in a monolithic integrated circuit. A signal coupler is integrated on a chip together with a primary circuit and a secondary circuit which is to be coupled to the primary circuit. The signal coupler comprises an integrated coupling capacitor which consists of a coplanar conductor path arrangement embedded into a passivation layer, the passivation layer being applied to an insulating substrate, preferably sapphire.

Monolithically integrated circuit of high dielectric strength for

A Schottky-transistor-logic arrangement is disclosed which comprises a highly doped semiconductor substrate of one conductivity type. An epitaxial layer of the same conductivity type is formed on the substrate. A deep-implanted doped zone of the other conductivity type is located in the epitaxial layer in a plane spaced below the outer surface of said epitaxial layer and lying substantially parallel thereto. A load transistor and an output transistor are formed by constructing the arrangement so that the buried layer provides the base of the load transistor and the emitter of the output transistor. The emitter of the load transistor is provided by a portion of the epitaxial layer which lies below the deep-implanted doped zone. The collector of the load transistor and the base of the output transistor are provided by the portion of the epitaxial layer which lies above the deep-implanted zone. A Schottky electrode on the outer surface of the epitaxial layer provides the collector of the output transistor. A plurality of Schottky diodes are also formed in a portion of the epitaxial layer which possess a lower Schottky barrier than the Schottky electrode of the output transistor.

Schottky-transistor-logic

An integrated current supply circuit is disclosed which utilizes a sub-circuit having a lambda-like current-voltage curve. Such a sub-circuit comprises a first field effect transistor whose source-drain path is connected to a series circuit formed from a load element and a second field effect transistor. The gate of the first field effect transistor is connected to the connection point of the load element and the second field effect transistor. A gate of the second FET leads either directly or via a voltage divider to the drain-side terminal of the series circuit. A capacitor is provided which is connected across output terminals of the circuit. The series circuit of the lambda sub-circuit is connected in parallel with input terminals, and the first FET connects between one of the input terminals and one of the output terminals.

Integrated current supply circuit

An arrangement is provided for supplying integrated injection logic (I.sup.2 L) circuits with differing currents. A first injector path is formed by a connection between an external supply voltage source and injectors of first I.sup.2 L circuits to be supplied with a first current. The first injector path is connected to the injecting emitter of a current hogging injection logic (CHIL) arrangement and a first input of the CHIL arrangement is connected to a second injector path formed by the connection to injectors of second I.sup.2 L circuits to be supplied with a second current.

Arrangement for supplying I.sup.2 L circuits with differing currents

An amplifier stage is provided for supplying differing currents to integrated injection logic I.sup.2 L circuits. The amplifier stage has a current hogging injection logic input CHIL gate, at least one further gate, and a CHIL output gate. Each of the gates has an injecting emitter, an output and an input. First I.sup.2 L circuits connected to a first injector path connect with the input of the CHIL input gate. Second I.sup.2 L circuits having a second injector path connect with an output of the CHIL output gate. The gate provided between the input and output CHIL gates is provided as a single I.sup.2 L gate, dual I.sup.2 L gates, or the combination of an I.sup.2 L gate and a CHIL gate.

Amplifier stage for the current supply of I.sup.2 L circuits

A lateral bipolar transistor has a silicon film which is epitaxially deposited on an electrical insulating substrate. The silicon film is doped with impurities of a first conductivity type such that a portion of the film may be utilized as a base zone. Within the base zone an emitter zone and a collector zone are formed of the second conductivity type. A highly doped zone of the second conductivity type is produced by deep implantation at a position which is contiguous and below the base zone, below the emitter and collector zones, and at a boundary between the silicon film and the electrical insulating substrate. An insulating zone over the film and a conductive layer over the base zone are also provided. The conductive film over the base zone together with the highly doped zone below and contiguous with the base minimize surface recombination and increase device gain.

Lateral bipolar transistor

A circuit arrangement CHL technique (current hogging logic) includes individual CHL arrangements each having an emitter, control collectors and an output collector and arranged within an epitaxial layer. The individual CHL arrangements are complementary with respect to one another, and arrangement of one conductivity type being directly integrated in the epitaxial layer and the arrangement which is complementary thereto being integrated in a basin in the epitaxial layer, the basin being doped opposite to the epitaxial layer.

Circuit arrangement in a complementary CHL technique

A logic circuit has the individual elements arranged in a semiconductor layer. The elements are in the form of field effect transistors having a multiple gate and bipolar transistors having a multiple emitter. The multiple gates of the field effect transistor represent the inputs of the fundamental logic circuit, and at least one emitter of the multiple emitters of the bipolar transistor represents the output of the fundamental logic circuit. The elements are arranged in the semiconductor layer in such a manner that a first supply voltage potential can be connected to the semiconductor layer. One configuration of the multiple gates of the field effect transistor identifies the circuit as a NAND circuit, while another configuration of the gates identifies the circuit as a NOR circuit. An additional element, a bipolar transistor, may be formed in the semiconductor layer and be connected to an emitter of the multiple emitter transistor to provide a power output stage in a Darlington configuration.

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Munich, Germany

Ruediger Mueller