Emc Corporation

Rudy M Bauer

Victor W Tung

Stephen Lawrence Scaringella

Brian Arsenault

Paul C Wilson

Stephen D MacArthur

Kenneth M Sullivan

William Frederick Baxter, Iii

An assembly couples first and second backplanes together. The first backplane is configured to carry first electrical backplane signals among a first set of circuit boards. The second backplane is configured to carry second electrical backplane signals among a second set of circuit boards. The assembly includes a first switch configured to convey at least some of the first electrical backplane signals between circuit boards of the first set of circuit boards. The assembly further includes a second switch configured to convey at least some of the second electrical backplane signals between circuit boards of the second set of circuit boards. The assembly further includes a fiber optic cable joining the first and second switches together. The first and second switches are configured to exchange fiber optic signals through the fiber optic cable thus forming a cohesive backplane interconnect system between the first and second sets of circuit boards.

Methods and apparatus for forming a cohesive backplane interconnect system

A computer storage system includes director boards which control transfer of data to and between a host computer, a system cache memory and a disk array. The directors are provided with features which enhance system performance and reliability. A hardware emulation controller permits a high performance processor to be used with existing system circuitry. A control store memory is organized with primary and secondary data areas and primary and secondary parity areas. Data is written to both the primary and secondary areas. A read request accesses data in the primary area and performs a retry in the secondary area in the event of a parity error. A power supply system includes on-board marginable power supplies to facilitate testing and power-up by-pass circuits for protection of sensitive circuitry. A system clock configuration employs primary and secondary clocks to ensure redundancy of synchronized timekeeping.

Computer storage system incorporating on-board EEPROMS containing product data

A system having a plurality of processors, each one of the processors being adapted to issue a control signal and a processor ID code. Each one of the processors has: a unique, pre-assigned processor ID code, and a common software program. The software program operates to: receive the control signal and the processor ID code from the issuing one of the processors along with an indication of the one of the processors which issued the particular control signal and processor ID code; and test whether the received processor ID code is the same as the processor issuing the command and if so, generate one of the broadcast mode or uni-cast modes; otherwise, generate the other one of the broadcast or uni-cast modes.

System having plural processors and a uni-cast/broadcast communication arrangement

A data storage system wherein a host computer is coupled to a bank of disk drives through an interface. The interface has a plurality of directors and a memory interconnected by a buss. The directors control data transfer between the host computer and the bank of disk drives as such data passes through the memory. The interface includes a plurality of ESCON adapters, a front end portion of the directors being coupled between the host computer and the busses through the ESCON adapters. Each one of such adapters includes a plurality of adapter ports each one being coupled to a corresponding port of the host computer. Each one of the adapters also includes a plurality of adapter board gate arrays and a plurality of optic interfaces. Each one of the optic interfaces is coupled between a corresponding one of the adapter port and a corresponding one of the adapter board gate arrays. Each coupled optic interfaces and gate array provides a corresponding one of a plurality of channels for the data. The adapter also includes a plurality of adapter board CPUs, each one being coupled to the adapter board gate arrays and the optic interface of a corresponding one of the channels. Each one of the CPUs controls the initiation and termination of the data passing through said corresponding one of the channels. Each one of the front end portion of the director boards includes a plurality of director board gate arrays and a plurality of EDACs. Each pair of the director board gate arrays is coupled between a corresponding pair of the adapter board gate arrays and a corresponding one of the EDACs. A plurality of director board CPUs is provided. Each one is coupled to a corresponding one of the adapter board CPUs. Each one of the director board CPUs is coupled to a corresponding one of the director board gate arrays to control the initiation and termination of a data transfer through such coupled one of the director gate arrays. A common state machine is coupled to the plurality of director gate arrays and the plurality of EDACs for arbitrating between the pair of director gate arrays coupled to the corresponding one of the EDACs for access to such corresponding one of the EDACs. Each one of the directors comprises: a plurality of dual port RAMs, each one being coupled to a corresponding one of the EDACs and to at least one of the busses. A second common state machine is coupled to the first common state machine and the plurality of dual port RAMs for arbitrating between the plurality of dual port RAMS for access to one the at least one of the busses.

Data storage system having director boards with plural processors

A method and apparatus for controlling the flow of data through director elements of a disk drive controller are responsive to external clock signals to synchronize the internal clock timing of each director. The external clock signals are available over either a first master bus or a secondary master bus, each of the buses being connected to the director element. Each director element has circuitry which monitors the occurrence of clock pulses over the buses as well as circuitry for switching, upon the occurrence of a failure of clock pulses on the master bus, from the master bus to the secondary bus for the receipt and resynchronization of clock pulses.

Disk drive controller for controlling data flow therethrough by switching to secondary bus to receive clock pulses when a failure on master bus is detected

A hardware emulation controller permits a high performance processor to be used with system circuitry that is configured for operation with a different processor. The hardware emulation controller is capable of modifying signals from the high performance processor for compatibility with the system circuitry. The hardware emulation controller is also capable of modifying signals from the system circuitry for compatibility with the high performance processor.

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Milford, MA, United States of America

Rudy M Bauer