International Business Machines Corporation

Globalfoundries Inc.

Rudolf Adriaan Haring

Martin Ohmacht

Alan G Gara

Thomas M Gooding

Paul William Coteus

Gerard Vincent Kopcsay

Dong Chen

Todd Edward Takken

Steven Michael Douskey

Mark Edwin Giampapa

Paul Gregory Crumley

Ralph E Bellofatto

Philip Heidelberger

Steven Frederick Oakland

Krishnan Sugavanam

Robert Matthew Senger

Matthew Roger Ellavsky

Don Darrell Reed

Arthur A Bright

Scott A Strissel

Marc B Dombrowa

Valentina Salapura

Michael Richard Ouellette

Bruce Martin Fleischer

Burkhard Steinmacher-Burow

Mark Gregory Megerian

Matthias Augustin Blumrich

Shawn Anthony Hall

George L Chiu

Noel A Eisley

Yutaka Sugawara

Thomas A Liebsch

Michael K Gschwind

Michael A Blocksome

Joseph D Ratterman

Adam James Muff

Chandramouli Visweswariah

Alexandre E Eichenberger

Robert William Wisniewski

John A Gunnels

Kathryn Mary O'Brien

Sameh W Asaad

Thomas Winters Fox

John Kevin O'Brien

Chen-Yong Cher

Barry Marshall Trager

Peng Wu

Charles David Wait

Terry I Chappell

Sameer Kumar

James Anthony Marcella

Todd Alan Inglett

Jeffrey John Parker

David L Satterfield

Douglas R Miller

Craig Brian Stunkel

Amith R Mamidala

Kristan D Davis

Jose R Brunheroto

Michael B Mundy

Andrew R Conn

Richard A Swetz

Robert E Walkup

James Lee Van Oosten

Samuel J Miller

Gabor J Dozsa

Ruth Janine Poole

Peter Boyle

Brant L Knudson

Norman Christ

Kahn C Evans

William Maupin Stockdell

Alfred Thomas Watson, Iii

Edward Seewann

James L Hedrick

Sang Hoo Dhong

Brian E Smith

Brian Samuel Beaman

Da-Yuan Shih

George Frederick Walker

Thomas Mario Cipolla

Mark James Jeanson

Xin Zhang

Barbara A Chappell

Michael Kevin Ciraula

Dietmar Schmunkamp

Mark S Milshtein

Talal K Jaber

Michael P Beakes

Juan Ayala-Esquilin

Brandon Edward Schenck

Daniel J Littrell

Lance G Hehenberger

Moyra Kathleen McManus

Michael Richard Quellette

Ralph A Bellofatto

Bryan J Weatherford

Talal Kamel Jaber

Max Eduardo De Ycaza

Pho Hoang Nguyen

An apparatus is disclosed that includes a semiconductor device to control a power converter having two or more power FETs. The semiconductor device includes a gate signal generator configured to produce two or more gate signals able to drive the two or more FETs. The gate signal generator has programmable timing configuration parameters to control operation of the two or more gate signals, wherein the timing configuration parameters are digitally programmed via a memory in the semiconductor device. The memory may be implemented with fuses, other non-volatile memory or volatile memory. The parameters may be fixed or updated during a lifetime of the apparatus. A serial-to-parallel conversion may be used to input the parameters. Optimization methods may be performed to determine parameters considered to be optimal. The apparatus may also include the power converter.

Integrated circuits with programmable gate timing signal generation for power converters and apparatus comprising the same

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.

Multi-petascale highly efficient parallel supercomputer

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.

An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.

System-wide power management control via clock distribution network

A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.

Testing and operating a multiprocessor chip with processor redundancy

Fixing a problem is usually greatly aided if the problem is reproducible. To ensure reproducibility of a multiprocessor system, the following aspects are proposed: a deterministic system start state, a single system clock, phase alignment of clocks in the system, system-wide synchronization events, reproducible execution of system components, deterministic chip interfaces, zero-impact communication with the system, precise stop of the system and a scan of the system state.

Reproducibility in a multiprocessor system

A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.

Global synchronization of parallel processors using clock pulse width modulation

An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software.

Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan

An apparatus and method for controlling power usage in a computer includes a plurality of computers communicating with a local control device, and a power source supplying power to the local control device and the computer. A plurality of sensors communicate with the computer for ascertaining power usage of the computer, and a system control device communicates with the computer for controlling power usage of the computer.

Power throttling of collections of computing elements

A massively parallel supercomputer of petaOPS-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC) having up to four processing elements. The ASIC nodes are interconnected by multiple independent networks that optimally maximize the throughput of packet communications between nodes with minimal latency. The multiple networks may include three high-speed networks for parallel algorithm message passing including a Torus, collective network, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. The use of a DMA engine is provided to facilitate message passing among the nodes without the expenditure of processing resources at the node.

Ultrascalable petaflop parallel supercomputer

A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Design structure for in-system redundant array repair in integrated circuits

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Method and apparatus for in-system redundant array repair on integrated circuits

A method of incorporating noise considerations during circuit optimization includes the steps of: specifying a circuit schematic to be optimized; specifying at least one noise criterion as a noise measurement, including the signal to be checked for noise, the sub-interval of time of interest, and the maximum allowable noise deviation; providing each noise criterion as either a semi-infinite constraint or a semi-infinite objective function; specifying at least one variable of the optimization; converting the semi-infinite noise constraints and the semi-infinite noise objective functions into time-integral equality constraints; optionally, if required, providing additional optimization criteria other than noise as, for each such criterion, either objective functions or constraints; creating a merit function to be minimized to solve the optimization problem; simulating the circuit in the time-domain; computing the values of the objective functions and constraints; efficiently computing the gradients of the merit function of the optimizer (including contributions of all objective functions and constraints and the time-integrals representing noise considerations) preferably by means of a single adjoint analysis; iteratively providing the constraint values, the objective function values and the gradients of the merit function to a nonlinear optimizer; and continuing the optimization iterations to convergence.

Method for incorporating noise considerations in automatic circuit

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Cortlandt Manor, NY, United States of America

Rudolf Adriaan Haring