Taiwan Semiconductor Manufacturing Comp. Ltd.

Ruchin Jain

Atul Katoch

Sanjeev Kumar Jain

Arun Achyuthan

Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. A sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior to the precharge of a second complementary bit line. The sleep signal may then precharge the bit lines of a second memory cell with further delay between the precharge of each bit line. The memory circuit is configured to precharge both bit lines of a memory cell at the same time when an operation associated with that cell is designated.

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Hsinchu, Taiwan

Ruchin Jain