Apple Inc.

3com Corporation

P.a. Semi, Inc.

Redback Networks Inc.

Ericsson Ab

Ruchi Wadhawan

Mark Hayter

George Kong Yiu

Zongjian Chen

Dominic Go

James B Keller

Sridhar Subramanian

Josh P De Cesare

Edmund G Chen

John Gregory Favor

Ryan E Hirth

Ramesh B Gunna

Michael J Smith

Bernard Joseph Semeria

Puneet Kumar

Jason M Kassoff

Sukalpa Biswas

Erik P Machnicki

Hao Chen

Gregory G Minshall

Craig Owens

James Han Wang

Christopher P Tann

Choon Ping Chng

Robert H Leonowich

Burton B Lo

Ravikrishna Cherukuri

Weichun Ku

Marwan A Fawal

Wen-Tsung Tang

Ayal Shoval

David A Kranzler

Kathleen Otis Lee

Don Yih Wong

Mark D Hayter

Michael Smith

Marc Hayter

Zongijan Chen

This application relates to performing seamless video transitions at a display panel when a video stream changes resolution and/or scale. The video stream can be provided by a host device to a timing controller (TCON). When a parameter of the video stream is going to change, the host device can cause the TCON to enter a panel self refresh (PSR) mode. During the PSR mode, the TCON can drive the display panel using an image frame stored in a memory of the TCON. Additionally, during the PSR mode, the host device can adjust a scaler and/or resolution associated with the TCON. Once the host device has finished adjusting the TCON, the TCON can exit the PSR mode and the host device can provide a new data stream to the TCON without any apparent display artifacts being output by the display panel.

Seamless video transitions

In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.

Interrupt distribution scheme

In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to schedule operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

Dynamic QoS upgrading

In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.

Power managed lock optimization

In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

Data transformation during direct memory access

DMA controller which performs DMA assist for one peripheral interface controller and DMA operation for another peripheral interface controller

DMA controller that passes destination pointers from transmit logic through a loopback buffer to receive logic to write data to memory

In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is not being cache but is being staged for retransmission on an interface to which the cache is coupled.

Cache used both as cache and staging buffer

Method and apparatus for generating DMA transfers to memory

In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.

Non-blocking address switch with shallow per agent queues

Growing community of inventors

Sunnyvale, CA, United States of America

Ruchi Wadhawan