Altera Corporation

Intel Corporation

Ru Yin Ng

Kuljit Singh Bains

David Wolk Mendel

Keith Duwel

Gary Brian Wallichs

Han Hua Leong

Chang Kian Tan

Saravanan Sethuraman

Geok Sun Chong

Per channel thermal management techniques are described herein. In one example, a memory controller receives channel temperature information for one or more channels of one or more dies in the stack. The memory controller can then throttle commands at a channel-level based on the channel temperature information. In one example, row commands and column commands to a channel are throttled at independent rates based on the channel temperature information. In one example, a row command throttling rate or column command throttling rate is based on a ratio of alternating on-time to off time of throttling signals, or a window of time in which commands are enabled or disabled to a channel. In one example, the row and column command throttling signals can be staggered across channels or pseudo channels.

Per channel thermal management techniques for stacked memory

A control system controls First-In First-Out (FIFO) settings of a receiving system. The control system includes a FIFO settings controller that receives a first signal indicative of a first frequency of data received by the receiving system. The FIFO settings controller receives a second signal indicative of a second frequency of a clock that reads the data received by the receiving system. The FIFO settings controller determines a difference (e.g., a parts-per-million (PPM) difference) between the first frequency and the second frequency. The FIFO settings controller sends a third signal indicative of instructions to adjust FIFO configuration settings based on the PPM difference.

Adaptive rate-matching first-in first-out (FIFO) system

An integrated circuit die includes interface and adapter circuits. The interface circuit exchanges data with an external device outside the integrated circuit die using a first clock signal. The interface circuit has a clock signal generation circuit to generate the first clock signal based on a second clock signal. The adapter circuit exchanges the data with the interface circuit. A frequency of the second clock signal is changed in response to an indication of a change in a data rate of the data. The adapter circuit causes the interface circuit to provide an adjustment to the first clock signal after the frequency of the second clock signal changes. The adapter circuit prevents the exchange of the data between the interface circuit and the external device until the adapter circuit receives an indication of completion of the adjustment to the first clock signal.

Techniques for clock rate changes during data rate changes in an integrated circuit (IC)

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Bayan Lepas, Malaysia

Ru Yin Ng