Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Haynes and Boone, Llp

Comp-any Gmbh

Ru-Gun Liu

Chih-Ming Lai

Ken-Hsien Hsieh

Wen-Chun Huang

Tsai-Sheng Gau

Shih-Ming Chang

Yung-Sung Yen

Wei-Liang Lin

Chih-Liang Chen

Charles Chew-Yuen Young

Chun-Kuang Chen

Ming-Feng Shieh

Jiann-Tyng Tzeng

Kam-Tou Sio

Chin-Hsiang Lin

Shau-Lin Shue

Chung-Ju Lee

Ya Hui Chang

Tien-I Bao

Shih-Wei Peng

Chia-Tien Wu

Kuei-Shun Chen

Lee-Chung Lu

Li-Te S Lin

Jyu-Horng Shieh

Wei-Cheng Lin

Burn Jeng Lin

Yung-Hsu Wu

Cheng-Hsiung Tsai

Yi-Hsiung Lin

Huang-Yu Chen

Yuan-Te Hou

Wei-Hao Wu

Chi-Cheng Hung

Cheng-Chi Chuang

Pinyen Lin

Jeng-Horng Chen

Yi-Kan Cheng

Chih-Wei Hsu

Shinn-Sheng Yu

Yu-Xuan Huang

Chia-Ying Lee

Hui-Zhong Zhuang

Li-Chun Tien

Ting-Wei Chiang

Shi Ning Ju

Tung-Heng Hsieh

Wen-Hao Chen

Jung-Chan Yang

Pin-Dai Sue

Yi-Nien Su

Guo-Huei Wu

Yen-Ming Chen

Tien-Lu Lin

Ching-Yu Chang

Ching-Wei Tsai

Chia-Hao Chang

Hai-Ching Chen

Tzu-Jin Yeh

Ho-Hsiang Chen

Hsiang-Huan Lee

Hua-Tai Lin

Chun-Yu Lin

Kuei Shun Chen

Ying-Ta Lu

Hua-Chou Tseng

Chii-Ping Chen

Sai-Hooi Yeong

Kuo-Cheng Ching

Kuo-Cheng Chiang

Chung-Te Lin

Huicheng Chang

Shy-Jay Lin

Dian-Hau Chen

Liang-Yin Chen

Chih-Yuan Ting

Chia-Cheng Chen

Chih-Chiang Tu

Hung-Chang Hsieh

Wen-Hao Cheng

Wen-Ju Preet Yang

De-Fang Chen

Min Cao

Chun-Yi Lee

Chien-Wei Wang

Horng-Huei Tseng

Li-Jui Chen

Mei-Yun Wang

Ziwei Fang

Anthony Yen

Huan-Just Lin

Yi-Hsun Chiu

Tzung-Chi Fu

Chao-Hsun Wang

Kuo-Yi Chao

Shang-Wen Chang

Chin-Chang Hsu

Ke-Ying Su

Chia-Hui Lin

Chi-Ming Tsai

A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.

Method of fabricating semiconductor device with reduced trench distortions

An integrated circuit includes a first and second active region, a first conductive structure, an insulating region, a set of gates and a set of contacts. The first and second active region are in a substrate, extend in a first direction, are located on a first level, and being separated from one another in a second direction. The first conductive structure extends in the first direction, is located on the first level, and is between the first and second active region. The insulating region is located on at least the first level, and is between the first and second active region and the first conductive structure. The set of gates extend in the second direction, overlap the first conductive structure, and is located on a second level. The set of contacts extend in the second direction, overlap the first conductive structure, and is located on the second level.

Integrated circuit and method of manufacturing same

The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes forming a hard mask layer over a substrate, the substrate having one or more regions to receive a treatment process, forming a resist layer over the hard mask layer, patterning the resist layer to form a plurality of openings in the resist layer, each of the openings free of concave corners, performing an opening expanding process to enlarge at least one of the openings in the resist layer, transferring the openings in the resist layer to the hard mask layer, and performing the treatment process to the one or more regions in the substrate through the openings in the hard mask layer.

Pattern fidelity enhancement

A semiconductor structure is provided and includes a first gate structure, a second gate structure, and at least one local interconnect that extend continuously across a non-active region from a first active region to a second active region. The semiconductor structure further includes a first separation spacer disposed on the first gate structure and first vias on the first gate structure. The first vias are arranged on opposite sides of the first separation spacer are isolated from each other and apart from the first separation spacer by different distances.

Semiconductor device including source/drain contact having height below gate stack

A method (of manufacturing conductors for a semiconductor device) includes: forming active regions (ARs) in a first layer, the ARs extending in a first direction; forming a conductive layer over the first layer; forming first, second and third caps over the conductive layer, the caps extending in a second direction perpendicular to the first direction, and the caps having corresponding first, second and third sensitivities that are different from each other; removing portions of the conductive layer not under the first, second or third caps resulting in gate electrodes under the first caps and first and second drain/source (D/S) electrodes correspondingly under the second or third caps; and selectively removing portions of corresponding ones of the first D/S electrodes and the second D/S electrodes.

Method of manufacturing conductors for semiconductor device

A method for mask data synthesis and mask making includes calibrating an optical proximity correction (OPC) model by adjusting a plurality of parameters including a first parameter and a second parameter, wherein the first parameter indicates a long-range effect caused by an electron-beam lithography tool for making a mask used to manufacture a structure, and the second parameter indicates a geometric feature of a structure or a manufacturing process to make the structure, generating a device layout, calculating a first grid pattern density map of the device layout, generating a long-range correction map, at least based on the calibrated OPC model and the first grid pattern density map of the device layout, and performing an OPC to generate a corrected mask layout, at least based on the generated long-range correction map and the calibrated OPC model.

Method of manufacturing integrated circuit

In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.

Method of manufacturing semiconductor devices

A method includes receiving a layout for fabricating a mask, determining a plurality of target contours corresponding to a plurality of sets of lithographic process conditions, determining a modification to the layout, simulating the modification to the layout under the plurality of sets of lithographic process conditions to produce a plurality of simulated contours, determining a cost of the modification to the layout based on comparisons between the plurality of simulated contours and corresponding ones in the plurality of target contours, and providing the modification to the layout for fabricating the mask based at least in part on the cost being within a predetermined threshold.

Optical proximity correction and photomasks

A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer.

Method of forming a semiconductor device

A method of manufacturing a semiconductor device includes dividing a number of dies along an x axis in a die matrix in each exposure field in an exposure field matrix delineated on the semiconductor substrate, wherein the x axis is parallel to one edge of a smallest rectangle enclosing the exposure field matrix. A number of dies is divided along a y axis in the die matrix, wherein the y axis is perpendicular to the x axis. Sequences SNx0, SNx1, SNx, SNxr, SNy0, SNy1, SNy, and SNyr are formed. p*(Nbx+1)−2 stepping operations are performed in a third direction and first sequence exposure/stepping/exposure operations and second sequence exposure/stepping/exposure operations are performed alternately between any two adjacent stepping operations as well as before a first stepping operation and after a last stepping operation. A distance of each stepping operation in order follows the sequence SNx.

Method of manufacturing a semiconductor device and apparatus for manufacturing the semiconductor device

In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.

Method of manufacturing semiconductor devices using directional process

Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.

Method for coloring circuit layout and system for performing the same

In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.

In accordance with an aspect of the present disclosure, in a pattern forming method for a semiconductor device, a first opening is formed in an underlying layer disposed over a substrate. The first opening is expanded in a first axis by directional etching to form a first groove in the underlying layer. A resist pattern is formed over the underlying layer. The resist pattern includes a second opening only partially overlapping the first groove. The underlying layer is patterned by using the resist pattern as an etching mask to form a second groove.

An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

Buried metal track and methods forming same

Growing community of inventors

Zhubei, Taiwan

Ru-Gun Liu