U.S. Philips Corporation

Nxp B.v.

Other

Royce Lowis

Brendan P Kelly

Paul T Moody

David J Coe

Edward S Eilley

Aart G Korteling

Peter M Tunbridge

Brendon P Kelly

Brendan P Kelley

A semiconductor device has a channel termination region for using a trenchfilled with field oxideand a channel stopper ringwhich extends from the first major surfacethrough p-wellalong the outer edgeof the trenchunder the trench and extends passed the inner edgeof the trench. This asymmetric channel stopper ring provides an effective termination to the channelwhich can extend as far as the trench

Method of forming a channel termination region using a trench and a channel stopper ring

A power semiconductor device is described with a plurality of cells divided into power cells () and sense cells (). A plurality of groups () of sense cells () are provided. The device allows for compensation of effects caused at the edges of the groups of sense cells ().

Semiconductor device with sense structure

A semiconductor device has a channel termination region for using a trench () filled with field oxide () and a channel stopper ring () which extends from the first major surface () through p-well () along the outer edge () of the trench (), under the trench and extends passed the inner edge () of the trench. This asymmetric channel stopper ring provides an effective termination to the channel () which can extend as far as the trench ().

Semiconductor device channel termination

A protected switch has a power semiconductor device (P) having first and second main electrodes (D and S) for coupling a load (L) between first (2) and second (3) voltage supply lines, a control electrode (G) coupled to a control voltage supply line (4) and a sense electrode (S1) for providing in operation of the power semiconductor device a sense current that flows between the first (d) and sense electrodes (S1) and is indicative of the current that flows between the first (D) and second (S) main electrodes. A control arrangement (S) has a sense resistance (R4) coupled to the sense electrode (S1) and across which a sense voltage is developed by the sense current (I.sub.3). A control semiconductor device (M3) has its main electrodes coupled between the control electrode (G) and the second (S) main electrode of the power semiconductor device (P). A semiconductor device (M2) has one (d) of its main electrodes coupled to the control electrode (g) of the control semiconductor device (M3) and the other (s) to the sense resistance (R4). A reference arrangement (50) provides a biasing voltage V.sub.b for the control electrode (g) of the semiconductor device (M2) to cause the semiconductor device (M2) to conduct sufficiently to cause the control semiconductor device (M3) to be non-conducting until the sense voltage reaches a reference voltage determined by the biasing voltage when the semiconductor device (M2) becomes less conducting, causing the control semiconductor device (M3) to start to conduct, so reducing the voltage at the control electrode (G) of the power semiconductor device (P) and thus reducing the current through the power semiconductor device (P).

Protected switch having a power semiconductor device

A temperature sensing circuit (100) for sensing the temperature of an active semiconductor device, for example, a power MOSFET (11) of a semiconductor body (10). The circuit has a first temperature sensing device (R1R2) provided on the semiconductor body at a first position (P.sub.1) adjacent a periphery (12) of the active semiconductor device (11), a second temperature sensing device (R3,R4) provided on the semiconductor body at a second position (P.sub.2) further from the periphery of the active semiconductor device than the first position. An arrangement, for example, a comparator responsive to the first and second temperature sensing devices provides a control signal to switch off the active semiconductor device (11) when the difference in the temperature sensed by the first and second sensing devices reaches a predetermined value.

Temperature sensing circuit

A semiconductor switch includes a power FET and a temperature sensor for providing a control signal to switch off the power FET when it reaches a predetermined thermal condition, such as a particular temperature. The power FET consists of a semiconductor body having a first region (13) of a first conductivity type adjacent one major surface (10a) thereof, and a plurality of cells (11). Each such cell has a second region (32) of the second (opposite) conductivity type provided within the first region (13), a third region (33) of the first conductivity type formed within the second region (32), and an insulated gate overlying a conduction channel in the second region (32) between the first and third regions (33 and 13). The temperature sensor (2) is formed within the semiconductor body (10) and consists of a number of further cells (11') of the same structure as the cells (11) of the power FET. The insulated gate of each further cell (11') is electrically connected to the third region (33') so as to form a parasitic bipolar transistor having a leakage current which varies with temperature, thereby enabling the temperature sensor to provide a control signal to switch off the power FET when the predetermined thermal condition is reached.

Semiconductor switch including a power transistor integrated with a

A temperature sensing circuit has a first insulated gate field effect device which is operated deep into its subthreshold region where the voltage across the device varies with temperature and has a second insulated gate field effect device which is operated in an area of its square law region where the voltage across the second insulated gate field effect device is substantially independent of temperature. A comparator compares the voltages across the first and second field effect devices and provides a signal OT indicating the temperature sensed by the first insulated gate field effect device.

An insulated-gate field-effect transistor which may be of the D-MOS or V-MOS type includes a source region (1) which is surrounded by a second region (2) of opposite conductivity type, itself surrounded by a third region (3) associated with the transistor drain (4). An insulated gate (12) of the transistor is present on a channel area of the second region (2) between the source region (1) and a first part (31) of the third region (3). The third region (3) also has a surface-adjoining second part (32) which is remote from the first part (31) and preferably has a lower doping concentration than the second and source regions (2, 1). An electrode layer (11) which may be the source electrode extends on said second part (32) of the third region (3) and is connected to said second region (2), and there is present between this electrode layer (11) and the second part (32) of the third region (3) a Schottky junction (33) having a lower forward voltage drop than the p-n junction (34) between the second and third regions (2,3). The transistor can have a fast switching speed even when driving inductive loads, since the Schottky junction (33) suppresses minority carrier injection at the forward-biased p-n junction (34) during voltage overswings. Preferably the second part (32) of the third region (3) is laterally bounded by the second region (2) which forms a guard ring for the Schottky junction (33) so maintaining a high blocking voltage capability. In order to further suppress minority carrier injection the electrode layer (11) preferably forms with the second region (2) a Schottky junction around which the source region (1) preferably extends as a guard ring.

Insulated-gate field-effect transistors

An insulated-gate field-effect transistor is disclosed which is particularly suitable for forming high-frequency transistors for a common source circuit configuration. The field-effect transistor is obtained in a simple and reliable manner using the following steps: (a) forming on an insulating layer a gate layer having separate, parallel apertures; (b) doping said epitaxial layer via said apertures so as to form parallel islands from which at least a portion of the source fingers is to be provided; (c) providing an etch-resistant mask having smaller parallel apertures each of which overlies an area of an island; (d) etching away said areas and underlying parts of the epitaxial layer so as to form parallel V-shaped grooves which expose the substrate, extend longitudinally along the islands and are adjoined along opposite sides by remaining parts of said islands, and (e) providing within the apertures of the gate layer and over the walls of the grooves parallel metal fingers which extend longitudinally along said islands to short-circuit the remaining parts of said islands to the epitaxial layer and to the substrate. These remaining parts form source fingers of the transistor. At least part of the drain fingers may also be formed in step (b).

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Stockport, United Kingdom

Royce Lowis