General Electric Company

Royal R Morse, Iii

Edward W Andrews

Arthur K Collins

Robert R Lijewski

Nallaswamy Srinivasan

Eugene W Bergholz

John E Celek

Bernard G Puerzer

A network interface equipment for a bus network employs separate processors and random-access memories for handling bus-protocol and data portions of a data packet. Each processor has access to a separate random-access memory to and from which it moves data. The random-access memories are multiple-ported to permit access by more than one requester with a logic arbitrator to resolve conflicts. A status random-access memory provides communication between the two processors.

Interface comprising message and protocol processors for interfacing

A system for writing cursors on a raster scanned television screen that uses the microprocessor in a display controller to produce blocks of data defining the parameters of vectors that compose the cursor. The blocks are put in a first-in first-out memory during a vertical blanking inerval or during active picture time. Each block specifies where writing of a cursor segment is to start and stop on a horizontal scan line and it also specifies a repeat count that indicates the number of lines on which the segment is to be written. Each block contains a delta value to indicate how much, if any each segment is to be displaced left or right from line to line so vertical and angulated vertical vectors can be produced. The blocks are read out of the memory consecutively by a circuit that converts the segment start and stop data to pixel counts. Pixel counters determine the writing start and stop points. When the number of horizontal lines on which segments are written equals the repeat count, the next block is processed.

Real-time cursor generator

A method of controlling a digital video processor in a digital fluorography system wherein the electronic components of the processor are variously configured to perform math functions and manipulations on digital image data obtained in connection with carrying out x-ray examination procedures and the images are displayed on a television monitor or recorded. A system controller sends a complete recipe for a procedure to the memory of a microprocessor based CPU that controls the video processor. The latter CPU interprets the instructions and effects configurations and reconfigurations in the data paths of the video processor during television vertical blanking intervals.

Digital fluorographic processor control

Growing community of inventors

Wales, WI, United States of America

Royal R Morse, Iii