International Business Machines Corporation

Sun Microsystems, Inc.

Oracle America, Inc.

Roy Stuart Moore

Edward Hugh Welbon

Frank Eliot Levine

Charles P Roth

Brian Walter O'Krafka

Pranay Koka

Warren Edward Maule

David Wayne Victor

Robert J Kroeger

Mary Ellen Mosher

The invention relates to a method for reducing cache flush time of a cache in a computer system. The method includes populating at least one of a plurality of directory entries of a dirty line directory based on modification of the cache to form at least one populated directory entry, and de-populating a pre-determined number of the plurality of directory entries according to a dirty line limiter protocol causing a write-back from the cache to a main memory, where the dirty line limiter protocol is based on a number of the at least one populated directory entry exceeding a pre-defined limit.

Reduction of cache flush time using a dirty line limiter

A method and system for detecting race conditions computing systems. A parallel computing system includes multiple processor cores is coupled to memory. An application with a code sequence in which parallelism to be exploited is executed on this system. Different processor cores may operate on a given memory line concurrently. Extra bits are associated with the memory data line and are used to indicate changes to corresponding subsections of data in the memory line. A memory controller may perform a comparison between check bits of a memory line to determine if more than one processor core modified the same section of data in a cache line and a race condition has occurred.

Hardware data race detection in HPCS codes

A circuit board including a signal transmission channel includes a dielectric substrate and a signal transmission channel which may be formed on the dielectric substrate. The signal transmission channel may include a conductor, a lossy dielectric material which may longitudinally encapsulate the conductor and a conductive material which may longitudinally encapsulate the lossy dielectric.

Circuit board including isolated signal transmission channels

A test system includes a device under test and a test circuit board. The device under test includes a plurality of contacts configured to provide output signals. The test circuit board may convey the output signals from the device under test to an analyzer. The test circuit board may include a dielectric layer, a via extending through the dielectric layer, a conductor formed on the dielectric layer and a resistive annular ring having a predetermined resistance value. The resistive annular ring may be formed around the via and may be electrically coupled between the via and the conductor.

Test system including a test circuit board including resistive devices

A system and method for correcting data errors. A system for correcting errors in blocks of data received over a communication medium includes an error history unit coupled to an error correction unit. The error history unit may maintain information associated with each bit position of the blocks of data in which a correctable error has occurred. The error correction unit may perform an error correction on a given block of data using an error correction code capable of correcting at least a single bit error and detecting multiple bit errors. Further, in response to detecting a multiple bit error, the error correction unit may correct subsequent errors in the given block of data dependent upon the information maintained by the error history unit.

System and method for correcting data errors

A method and implementing system are provided in which a service processor is implemented in addition to system processors. The service processor is enabled to access system on-chip registers to acquire system data through the use of the system JTAG bus connections. In one embodiment, logic is provided to determine concurrent calls for use of the same registers by both the system processor(s) and also by the service processor through the JTAG bus. In case of concurrent requests, the JTAG data are held so as not to interfere with system operations until the system processor's use of the registers has been completed.

Method and apparatus of resolving conflicting register access requests from a service processor and system processor

A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.

Performance monitoring of cache misses and instructions completed for instruction parallelism analysis

CPI infinite and finite analysis

A processor operable for processing an instruction through a plurality of internal stages will produce a result of the processing of the process at each stage or a reason code why the stage was unable to process the instruction. The result or the reason code will then be passed to a subsequent stage, which will attempt to process the instruction. The second stage will forward the reason code when it cannot produce its own result and it is idle. The second stage will create its own reason code when it is not idle but cannot produce a result, and will forward this reason code.

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Austin, TX, United States of America

Roy Stuart Moore