Apple Inc.

Roy Roth

Yonathan Tate

Nir Tishbi

Ruby Mizrahi

Ilia Benkovitch

Michael Jeffet

A memory controller includes an interface and a processor. The interface is configured to communicate with a plurality of memory cells. The processor is configured to, using multiple Read Thresholds (RTs) positioned between adjacent Programming Voltages (PVs), produce (i) a base parametric model of Threshold Voltage Distributions (TVDs) associated with the PVs, and (ii) auxiliary information that depends on the RTs and on the base parametric model, to read a group of the memory cells using the RTs to produce multiple readouts, the threshold voltages of the memory cells in the group are distributed in accordance with actual TVDs, to derive from the base parametric model an actual parametric model, based on the multiple readouts and on the auxiliary information, and determine a readout parameter based on the actual parametric model, and to perform a read-related operation using the readout parameter.

Readout from memory cells subjected to perturbations in threshold voltage distributions

A decoder includes circuitry and multiple Variable-Node Circuits (VNCs). The VNCs individually hold one or more variables of an Error Correction Code (ECC) that is representable by a plurality of check equations defined over the variables. The circuitry is configured to receive a code word including variables having m-bit values that was encoded using the ECC, to further receive reliability levels assigned respectively to the variables, to decode the code word by applying to the code word a sequence of iterations, including deciding in a given iteration whether a given VNC is to be processed or skipped in that iteration, depending on the reliability levels assigned to the variables of the given VNC, and, when the given VNC is selected for processing, to make a decision whether or not to update one or more of the variables of the given VNC, and to apply the decision by the given VNC.

Scheduling of iterative decoding depending on soft inputs

A memory controller includes an interface and a processor. The interface communicates with a plurality of memory cells, and an individual one of the plurality of memory cells stores data in multiple predefined programming levels. The processor is configured to read an Error Correction Code (ECC) code word from a group of memory cells, via the interface, using multiple read thresholds positioned between adjacent programming levels, for producing multiple readouts that contain respective numbers of errors, to derive from the code word a reference readout that contains no errors, or contains a number of errors smaller than in the code word, to calculate multiple distances between the reference readout and the respective readouts, and set a preferred read threshold based on the calculated distances, and to perform subsequent read operations for retrieving data from the plurality of memory cells, using the preferred read threshold.

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Tel Aviv, Israel

Roy Roth