International Business Machines Corporation

Yale University

Globalfoundries U.S. 2 LLC

Roy Rongqing Yu

Emily R Kinser

Sampath Purushothaman

Chandrika Prasad

Steven J Holmes

Qinghuang Lin

H Bernhard Pogge

Kimberley A Kelly

Hariklia Deligianni

Nathan P Marchack

Eric D Perfecto

Arthur Gilman Merryman

Mukta G Farooq

Subramanian Srikanteswara Iyer

Steven John Koester

Robert Hannon

Albert M Young

Bruce Bennett Doris

Thomas Anthony Wassick

John Ulrich Knickerbocker

Fei Liu

Bouwe W Leenstra

Peter A Franklin

Deborah A Neumayer

Chandrasekhar Narayan

Mary Beth Rothwell

William Harrington Brearley

Ashwani K Malhotra

Mary Elizabeth Rothwell

Ruilong Xie

Ghavam G Shahidi

Balasubramanian Pranatharthiharan

Evan G Colgan

Takeshi Nogami

Wilfried Haensch

Sufi Zafar

Huan Hu

Stacey M Gifford

Ajay Prabhakar Giri

James J Bucchignano

James L Hedrick

Robert Dennis Miller

Gerald Keith Bartley

Laertis Economikos

Damon B Farmer

Willi Volksen

Suryanarayana Kaja

Kurt A Smith

Kamalesh S Desai

Paul F Findeis

Kangguo Cheng

Brent A Anderson

Daniel C Edelstein

Voya Rista Markovich

Julien Frougier

Wu-Song S Huang

Pushkara Rao Varanasi

Michel Despont

Peter Vettiger

Lewis Sigmund Goldmann

Tien-Jen Cheng

Ute Drechsler

Giulio DiGiacomo

Gerald Warren Gibson, Jr

Chih-Chao Yang

Devendra K Sadana

Ning Li

Timothy Joseph Dalton

Michael A Gaynes

Matthew Earl Colburn

Bucknell Chapman Webb

Elbert Emin Huang

Sri Muthuthamby Sri-Jayantha

Kisik Choi

Thomas M Shaw

Satyanarayana Venkata Nitta

Robert L Wisnieff

Donald Seton Farquhar

Katsuyuki Sakuma

Jeffrey Curtis Hedrick

Steven Alan Cordes

Kwong Hon Wong

Sung Kwon Kang

Shyng-Tsong Chen

Vijayeshwar Das Khanna

Kaushik Arun Kumar

Mark David Poliks

Michael Wayne Lane

Christy Sensenich Tyberg

Robert Anthony Rita

Ko-Tao Lee

Yu Luo

Kelly Malone

Monty Montague Denneau

Mukta S Farooq

Harvey Charles Hamel

Raymond Thomas Galasco

Srinivasa S N Reddy

Peter Jerome Sorce

Stefanie Ruth Chiras

An apparatus for bonding a first substrate to a second substrate includes a heatable mounting stage configured to accommodate a first semiconductor substrate on an upward-facing surface and a first stack of semiconductor materials on the first semiconductor substrate; a heatable bond head configured to accommodate a second semiconductor substrate on a downward-facing surface and a second stack of semiconductor materials on the second semiconductor substrate; and a collet disposed on the downward-facing surface of the heatable bond head and configured to receive the second semiconductor substrate and the second stack of semiconductor materials. The heatable bond head is configured to have a vacuum applied thereto to deformably accommodate the second semiconductor substrate and the second stack of semiconductor materials against the collet. The heatable bond head is configured to be pressed against the heatable mounting stage to bond the semiconductor materials.

Structures and processes for void-free hybrid bonding

A semiconductor device includes a dielectric isolation layer, a plurality of gates formed above the dielectric isolation layer, a plurality of source/drain regions above the dielectric isolation layer between the plurality of gates, and at least one contact placeholder for a backside contact. The at least one contact placeholder contacts a bottom surface of a first source/drain region of the plurality of source/drain regions. The semiconductor device further includes at least one backside contact contacting a bottom surface of a second source/drain region of the plurality of source/drain regions, and a buried power rail arranged beneath, and contacting the at least one backside contact.

Backside electrical contacts to buried power rails

A method of manufacturing a semiconductor device is provided. The method includes forming a first recess partially through a substrate from a first side of the substrate, forming a dielectric layer in the first recess, forming a second recess partially through the dielectric layer from the first side of the substrate, and forming a buried power rail (BPR) in the second recess of the dielectric layer. The method also includes thinning the substrate from a second side of the substrate to a level of the dielectric layer, the second side of the substrate being opposite to the first side of the substrate.

Substrate thinning for a backside power distribution network

A structure for monitoring and stimulation includes an external power supply unit. The structure also includes an internal hub communicatively coupled to the external power supply unit. The structure further includes a plurality of sensor modules communicatively coupled to the internal hub by a plurality of flexible interconnects. The plurality of sensor modules include three-dimensional (3D) comb sensor devices.

Three-dimensional silicon-based comb probe with optimized biocompatible dimensions for neural sensing and stimulation

A method of fabricating a semiconductor device comprises forming backside power rails in a dielectric layer arranged above a backside interlayer dielectric (BILD) layer or a semiconductor layer, forming a trench that extends through the BILD layer or the semiconductor layer and partly through the dielectric layer between the backside power rails, depositing a plurality of layers to form a backside metal-insulator-metal (MIM) capacitor in the trench, and forming a first contact to a first metal layer of the plurality of layers. Forming the first contact comprises forming first recesses in a second metal layer of the plurality of layers, and filling the first recesses with an insulative material. The method further comprises forming a second contact to the second metal layer. Forming the second contact comprises forming second recesses in the first metal layer, and filling the second recesses with the insulative material.

Backside metal-insulator-metal (MIM) capacitors extending through backside interlayer dielectric (BILD) layer or semiconductor layer and partly through dielectric layer

A nanostructure includes a base layer including a surface. The nanostructure further includes nano-patterned features including non-random topography located on the surface of the base layer. The nanostructure also includes an encapsulating layer including a conductive material arranged on the nano-patterned features.

Nanostructure featuring nano-topography with optimized electrical and biochemical properties

A method of manufacturing a semiconductor device is provided. The method includes forming a first trench partially through a first substrate from a first side of the first substrate. The method also includes widening a bottom portion of the first trench to form a lateral footing area of the first trench. The method includes forming a first metallization in the first trench; forming a second trench through a second substrate from a second side of the second substrate to expose at least a portion of first metallization in an area corresponding to the lateral footing area of the first trench, the second side being opposite to the first side. The method also includes forming a second metallization in the second trench in contact with the first metallization.

Backside power rail integration

A method for forming a nanostructure includes coating an exposed surface of a base layer with a patterning layer. The method further includes forming a pattern in the patterning layer including nano-patterned non-random openings, such that a bottom portion of the non-random openings provides direct access to the exposed surface of the base layer. The method also includes depositing a material in the non-random openings in the patterning layer, such that the material contacts the exposed surface to produce repeating individually articulated nano-scale features. The method includes removing remaining portions of the patterning layer. The method further includes forming an encapsulation layer on exposed surfaces of the repeating individually articulated nanoscale features and the exposed surface of the base layer.

Technical solutions are described for implementing an optogenetics treatment using a probe and probe controller are described. A probe controller controls a probe to perform the method that includes emitting, by a light source of the probe, the probe is embeddable in a tissue, a light wave to interact with a corresponding chemical in one or more cells in the tissue. The method further includes capturing, by a sensor of the probe, a spectroscopy of the light wave interacting with the corresponding chemical. The method further includes sending, by the probe, the spectroscopy to an analysis system. The method further includes receiving, by the probe, from the analysis system, adjusted parameters for the light source, and adjusting, by a controller of the probe, settings of the light source according to the received adjusted parameters to emit a different light wave to interact with the corresponding chemical.

Cognitive optogenetics probe and analysis

A 4D device comprises a 2D multi-core logic and a 3D memory stack connected through the memory stack sidewall using a fine pitch T&J connection. The 3D memory in the stack is thinned from the original wafer thickness to no remaining Si. A tongue and groove device at the memory wafer top and bottom surfaces allows an accurate stack alignment. The memory stack also has micro-channels on the backside to allow fluid cooling. The memory stack is further diced at the fixed clock-cycle distance and is flipped on its side and re-assembled on to a template into a pseudo-wafer format. The top side wall of the assembly is polished and built with BEOL to fan-out and use the T&J fine pitch connection to join to the 2D logic wafer. The other side of the memory stack is polished, fanned-out, and bumped with C4 solder. The invention also comprises a process for manufacturing the device. In another aspect, the invention comprises a 4D process and device for over 50&#xd7; greater than 2D memory density per die and an ultra high density memory.

Four D device process and structure

A three-dimensional (3D) comb probe structure includes a carrier, a plurality of combs arranged in the carrier and spaced apart from one another, a plurality of shanks forming the combs, each shank including a base portion and a stem portion extending from the base portion, wherein sets of the shanks are joined together by the base portions thereof to form a respective comb, and a plurality of sensing elements disposed along the stem portion of each of the shanks and electrically connected to electrical contacts disposed at respective ones of the base portions. The sensing elements can include nanopatterned features on surfaces thereof forming a non-random topography.

Three-dimensional silicon-based comb probe

A biosensor includes an array of metal nanorods formed on a substrate. An electropolymerized conductor is formed over tops of a portion of the nanorods to form a reservoir between the electropolymerized conductor and the substrate. The electropolymerized conductor includes pores that open and close responsively to electrical signals applied to the nanorods. A dispensing material is loaded in the reservoir to be dispersed in accordance with open pores.

Neuro-chemical sensor with inhibition of fouling on nano-electrode

A sensing and treatment device includes an array of metal nanorod electrodes formed on a substrate, the array including first electrodes for sensing, and second electrodes for electrical pulsation. A data processing system is configured to monitor a parameter using the first electrodes and to activate the electrical pulsation in the second electrodes in accordance with a reading of the parameter.

Intelligent and disposable device for selective electrical stimulation of apoptosis

The present invention relates to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.

Enhanced adhesive materials and processes for 3D applications

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Poughkeepsie, NY, United States of America

Roy Rongqing Yu