Burroughs, Inc.

Unisys Corporation

Roy R Shanks

Richard J Petschauer

Jonathan A Levi

Cevat Kumbasar

Michael J Mahon

Steven S Wei

An integrated circuit test wafer quickly detects A-C defects in any process by which the wafer is fabricated. This test wafer includes a semiconductor substrate having a major surface, and a diagnostic circuit that is repeatedly integrated over most of the wafer's surface. Each diagnostic circuit includes: a) a plurality of ring oscillators which generate respective cyclic output signals; b) an addressing circuit that receives external input signals and in response selects an output signal from any particular ring oscillator of the plurality; c) a timing circuit that generates a timing signal with a certain time period; and, d) a counting circuit that counts the number of cycles that occur in the selected output signal during the time period and provides that number as an output. By comparing the relative or absolute speeds of all of the ring oscillators, a ring oscillator with an A-C defect is detected; and, a defective ring oscillator can then be analyzed under an E-beam microscope to determine the defects cause. Preferably, the ring oscillators occupy at least 90% of the test wafers surface so that A-C defects are detected even when they are sparsely distributed on the test wafer.

Test wafer for diagnosing flaws in an integrated circuit fabrication

This disclosure relates to a controlled selective power disconnect means for employment with the various circuits implemented on a crystalline wafer so that a particular circuit can be selectively disconnected when it has developed a defect or short or is unwanted in the system for other reasons. The disconnect means employs a gate between the power source and the circuit, which gate is controlled by a fuse that can be melted or blown by a power disconnect signal thereby opening the gate. An amorphous switch can also be used such that networks can expand or contract around defective chips as required by the particular task or tasks involved.

Controlled selective disconnect system for wafer scale integrated

This disclosure relates to a thin film amorphous memory cell which can be fabricated upon the surface of a semiconductor substrate in such a manner as to minimize the surface area requirements for each cell thereby increase the packing density of the memory array. Furthermore, since the cell can be fabricated on top of the semiconductor substrate, other active devices can be fabricated in the substrate so as to further increase the packing density of the integrated circuit chip containing memory array or other circuits. The memory cell is formed of a thin film diode of one or more amorphous semiconductor layers that are doped to form either a PN junction diode or, with one such layer, a Schottky diode, and the memory cell includes an amorphous layer of a tellurium based chalcogenide material that may be employed in either a memory mode or a threshold mode so that the memory cell may be operated in either a non-volatile or volatile manner.

Thin film memory device employing amorphous semiconductor materials

A single transistor memory cell wherein the memory cell is provided by the base collector capacitance of the transistor in the integrated circuit chip. Mounted on top the chip in electrical contact with the base of the transistor is an amorphous semiconductor threshold device employing a tellurium based chalcogenide such that when a charge is applied to the terminal of the device opposite the transistor base, the device will be switched to a high conducting state until such time as the base collector capacitance has been charged and then the threshold device will be switched to a low-conducting state. Specifically, the amorphous threshold device employs Ge.sub.15 Te.sub.81 Sb.sub.2 S.sub.2.

Growing community of inventors

San Diego, CA, United States of America

Roy R Shanks