Lsi Logic Corporation

Roy Perrigo

Jonathan W Byrn

James Arnold Jensen

Donald Gabrielson

The present invention is directed to a method and an apparatus for automatically configuring and/or inserting chip resources for manufacturing tests. A maximum test configuration ('test backplane') for all IP blocks is created and loaded into a tool suite. When a user issues a request to consume some IP blocks, the request may be checked for legality within the 'test backplane'. If a test resource (IP block) is not available for activation, then either the test resource may not be activated or the conflicting resource problem must be resolved so that the test resource may be activated. This may avoid late design surprises. The resources on the platform may already have test structures associated with them. All of these test structures may be associated with the &#x201c;test backplane&#x201d;. These pre-exiting test structures may then be connected.

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Henrietta, NY, United States of America

Roy Perrigo