Intel Corporation

Ncr Corporation

Roy M Stevens

Gene F Young

Larry C James

John H Crawford

Brian S Morris

Suneeta Sah

Sreenivas Mandava

Mathew W Stefaniw

Ted Rossin

Edward A McDonald

Richard I Mellitz

Arthur F Cochcroft, Jr

Byron L Reams

Billy K Taylor

Richard R Barton

Robert J Miller

Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.

Techniques for determining victim row addresses in a volatile memory

A computer system includes a cache memory which is shared by multiple processors. The cache memory is divided into a plurality of regions. Each of the processor is exclusively associated with one or more of the regions. All the processors have access to all regions on hits. However, on misses, a processor can cause memory allocation only within its associated region or regions. This means that a processor can cause memory allocation only over data it had fetched. By such arrangement, the &ldquo;cross-thrash&rdquo; problem is avoided.

Apparatus and method for selectively allocating cache lines in a partitioned cache shared by multiprocessors

Method and apparatus for using one bit per line of system memory to maintain coherency in a dual-ported memory system. The states of the bit are 'Owned' and 'Unowned.' The state of the bit is used to filter the number of cycles required to maintain coherency. The bits are stored within the system memory.

Directory-based coherency system for maintaining coherency in a

A branched transmission line, used for delivering control signals to integrated memory circuits. Memory circuits require control signals, which are delivered on control lines. If multiple memory circuits are involved, multiple control lines are used. If the multiple control lines branch from a common branch point on a supply line, undesirable reflections can occur. The invention reduces the reflections, by distributing the branching, as by starting with three initial branches, each of which branches into three other branches, in order to feed nine memory circuits.

Transmission line system for printed circuits

A multiprocessor computing apparatus that includes a mechanism for favoring at least one processor over another processor to achieve more equitable access to cached data. Logic for detecting when, for example, a remote and a local processor are attempting to access data from the cache of another local processor is disclosed. Logic that provides an advantage to the remote processor in a manner that achieves fairer access among the various processors is also disclosed.

Multiprocessor computing apparatus having spin lock fairness

An improved directory-based cache coherency memory system for a multiprocessor computer system. The memory system includes a dual ported system memory shared by the multiple processors within the computer system; a plurality of data cache memories, at least one data cache memory associated with each processor; and first and second memory busses, the first memory bus connecting a first subset of processors and associated data cache memories to a first port (PORT A) of the system memory, and the second memory bus connecting a second subset of processors and associated data cache memories to a second port (PORT B) of the system memory. Cache coherency is maintained through the use of memory line state information saved with each line of memory within the system memory and data cache memories. The system memory contains a system memory line state for each line of memory saved within the system memory, the system memory line state being any one of the group: SHARED PORT A, SHARED BOTH, OWNED PORT A and OWNED PORT B. Each one of these states is represented by a different two bit code saved with each line of memory in system memory. Additionally, each data cache memory contains a data cache memory line state for each line of memory saved within the data cache memory, the data cache memory line state being any one of the group: MODIFIED, EXCLUSIVE, SHARED, or INVALID.

Directory-based coherency system using two bits to maintain coherency on

A directory-based cache coherency memory system for a multiprocessor computer system. The memory system includes a system memory shared by the multiple processors within the computer system; a plurality of data cache memories, at least one data cache memory associated with each processor; a system of busses interconnecting the system memory with the plurality of data cache memories and processors, and a state cache memory associated with the shared system memory for the storage of memory line state information identifying where within the system memory and the plurality of data cache memories the most current copy of a line of memory resides. The state cache memory is sized to store state information for only a portion of the memory lines included in system memory, e.g., one sixteenth of the memory lines contained in system memory, in recognition that rarely will all of system memory be utilized (cached) at any one time. The state cache can be a direct mapped cache wherein state information for an associated line of memory is stored within the state cache together with a tag field being a first portion of the address of the associated line of memory, and indexed within the state cache by the remaining portion of the address.

Method and apparatus for caching state information within a

An improved method for performing state cache line replacement operations in a multiprocessor computer system including plurality if data cache memories, a shared system memory, a state cache memory, and employing a centralized/distributed directory-based cache coherency system for maintaining consistency between lines of memory within the shared system memory and the plurality of data cache memories. The method for performing state cache line replacement operations includes the steps of: establishing a default system memory line state of SHARED for lines of memory represented in said state cache memory; reading the system memory line state for a previously stored state cache entry prior to a replacement of said previously stored state cache entry, said previously stored state cache entry being associated with a line of memory stored in said shared memory and at least one data cache memory; and performing a castout operation to update the line of memory within said shared memory and assigning a data cache memory line state of SHARED to said line of memory in each data cache memory containing said line of memory if said system memory line state for said previously stored state cache entry is OWNED. Since most lines of memory are in a shared state prior to replacement, setting the default state to a shared state, rather than a uncached state, reduces the number of invalidate coherency operations which must be performed during state cache line replacements.

Growing community of inventors

Lexington, SC, United States of America

Roy M Stevens