Nxp Usa, Inc.

Freescale Semiconductor,inc.

Roy M Shor

Ori Goren

Avraham Horn

John J Vaglica

Amit Gur

Tuongvu Van Nguyen

Arvind Kaushik

Somvir Dahiya

Odi Dahan

Arindam Sinha

Shay Shpritz

Nir Baruch

Igor Shoihet

Yael Kahil

Ofer Lent

Avraham Rabinovich

Gad Yuval

Puneet Wadhawan

Interfacing between radio units in a base station in a mobile communication system uses a common public radio interface CPRI for streaming IQ data samples and control data arranged in lanes. A separate serial interface sRIO is now additionally used for transferring selected control data arranged in packets to a controller, the selected control data being streamed between other radio units via the common public radio interface. In the radio unit, the selected control data are arranged in packets to be transmitted via the serial interface, and, vice versa, the selected control data arranged in packets received via the serial interface are arranged in lanes to be streamed. Advantageously the control data of the streaming CPRI interface is seamlessly transferred to the controller via the packet based serial interface.

Method and device for streaming control data in a mobile communication system

Interfacing between radio units in a base station in a mobile communication system uses a common public radio interface CPRI for streaming IQ data samples arranged in lanes. A separate serial interface sRIO is now additionally used for transferring selected data samples arranged in packets, the selected samples corresponding to selected lanes streamed between other radio units via the common public radio interface. In the radio unit, the selected data samples are arranged in packets to be transmitted via the serial interface, and, vice versa, the selected data samples arranged in packets received via the serial interface are arranged in lanes. A system timer coupled to the CPRI generates a timebase for controlling the sRIO interface in order to have it synchronized. Advantageously the data sample transfer capacity of the streaming CPRI interface is extended using the packet based serial interface.

Method and device for data streaming in a mobile communication system

A system for use in nodes communicating over a CPRI (common public radio interface) allows each networking node in a daisychain configuration to seamlessly manage the control and management HDLC (high-speed data link control) channel for both uplink and downlink. The connection is kept alive through a soft reset flow. Received HDLC packets can be extracted for use by a local node. Locally generated packets can be inserted into the packet data stream at the datalink layer for onward transmission over the CPRI. The system arbitrates between the locally generated packet data held in a buffer in the local node and remote packet data received from a remote node and held in the local node in a first in first out buffer for onward transmission to a subsequent node after arbitration. Remote packet data is given priority.

Apparatus, system and method for controlling packet data flow

A method of recovery from a time-synchronization loss in a communication unit between a first processor supporting physical layer communications and a second processor supporting layer-2 communications is described. The method comprises: detecting, by the first processor, that a loss of sync has occurred between the first and second processors; in response to said detecting, stopping sending subsequent physical layer messages from the first processor to the second processor, for example to allow the second processor to consume any old pending messages; re-starting a messaging process by the first processor by sending at least one new message to the second processor with updated System Frame Number, SFN, and Sub-Frame, SF, counter value; and receiving at the first processor at least one subsequent response message from the second processor acknowledging receipt of at least one new message with an indication of the received and updated SFN and SF counter value of that message thereby confirming synchronization being restored.

Method for determining and recovering from loss of synchronization, communication units and integrated circuits therefor

A processor device processes data samples of a radio signal in a mobile communication system. A fast flow process is executed for all samples and a batch process is executed at intervals on a subset of the samples. The device has a processor for executing the flow process via a local buffer memory, a memory interface to a system memory, and a memory controller for controlling storing of the data samples in the buffer memory. The processor establishes whether data samples in the local buffer memory are part of the subset, and if not, invalidates them after executing the flow process. The memory controller provides free memory space in the local buffer by transferring data samples which are not invalidated from the local buffer memory to the system memory, and by invalidating processed samples. Advantageously the local buffer may be relatively small, while the amount of data transferred to the system memory is limited.

Device and method for processing in a mobile communication system

A Common Public Radio Interface, CPRI, lane controller of a processor, in a Time Division Duplex, TDD, system, said CPRI lane controller comprising: a Direct Memory Access (or more than one), DMA, controller connected to a memory through a switch fabric to perform read or/and write memory access transactions via an internal system bus of said processor, wherein said DMA controller is adapted to generate a RX/TX transaction interrupt(s) for each completed memory access RX/TX transaction counted by a corresponding transaction counter(s) which provides a TDD slot awareness interrupt(s) when a RX/TX TDD slot has terminated, wherein said DMA controller has a steering control(s) adapted to steer the memory access transactions either to said memory or to be legitimately blocked by said switch fabric in response to said TDD slot awareness interrupt(s) to save bandwidth, BW, of the internal system bus of said processor.

Common public radio interface (CPRI) lane controller coupled to direct memory access (DMA) wherein a time division duplex (TDD) steers control of CPRI

Interfacing according to a common public radio interface in a base station in a mobile communication system is described. The interfacing comprises a conversion process for rate-converting legacy data samples. First a predetermined number of the legacy data samples is converted to frequency samples in a frequency domain, then the frequency samples are zero padded to extend the frequency range according to a related sample rate of a 4G data format and then converted into a number of data samples of the related sample rate. The related sample rate is a multiplication of S/K times a basic frame rate of the 4G data format, S samples being allocated to K frames, K and S being integers and K being 8 or less. Advantageously large buffers for allocating a large number of legacy samples to 4G frames are avoided.

Method and device for interfacing in a mobile communication system

An apparatus for facilitating the re-distribution of processing load between a plurality of radio equipment controllers arranged in a daisy chain configuration on a Common Public Radio Interface. The apparatus may be included in each REC and has two framers which may co-operate to forward IQ data of antenna carriers received on a downlink from a preceding REC to a subsequent REC in the chain and a DMA module or channel which can read IQ data from a system memory for onward transmission. In a re-allocation mode, the framer may be reconfigured so that an AxC initially allocated to a preceding REC for processing may be instead, accessed by a second (usually redundant) transmit DMA module included in the apparatus from system memory and transferred to the framer for onward transmission.

Method and apparatus for processing data flows

A digital signal processor (), compatible with the Common Public Radio Interface (CPRI), permits reading and writing of IQ data of antenna carriers which have two different sampling rates by using just two single sample rate DMA (Direct Memory Access) modules (). The digital signal processor () is capable of processing data of different sampling rates on just one CPRI lane comprising one framer (). This is achieved by incorporating a divider module () and a multiplexer module () between the framer () and system memory (). The processor () may also be configured so that single sampling rates can also be accommodated.

System and method for processing data flows

A method and apparatus automatically controls the insertion of information flow data over a shared CPRI link () by providing a hardware control mechanism (-) at a local radio base station subsystem () connected in a CPRI daisy chain configuration between a downstream RE device () and an upstream REC device () for determining whether the control word being transmitted is sourced from a downstream device (e.g., forwarded data from a downstream RE device) or from the local device.

Method and system for automatically controlling the insertion of control word in CPRI daisy chain configuration

The method and system supports multiple bandwidth traffic over a single CPRI (common public radio interface) link () using a single bandwidth DMA (direct memory access) engine () and fast Fourier transform/inverse fast Fourier transform processing. () The invention exploits fast Fourier transform/inverse fast Fourier transform properties and is particularly suitable for supporting LTE (Long Term Evolution) cellular communication systems () The CPRI Media Access Control is configured in each CPRI lane to run at the maximum bandwidth among the bandwidths required. In the uplink, lower bandwidth data samples are padded with zeros and flexible positioning may be used to arrange the data in a CPRI frame. In the downlink, the radio equipment receiver () only processes the relevant data and ignores any interpolated samples. The invention is compatible with CPRI and LTE standards.

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Israel, Israel

Roy M Shor