Agilent Technologies, Inc.

Hewlett-Packard Company

Roy H Williams

Aik Koon Loh

Tiam Hock Tan

Daniel Z Whang

Chen Ni Low

Keen Fung Wai

Yi Jin

Tiam Hock Joseph Tan

Ellis Yuan

Keen Fung Jason Wai

Rex Shang

A method and apparatus for automatically debugging and optimizing an in-circuit test that is used to test a device under test on an automated tester is presented. The novel test debug and optimization technique extracts expert knowledge contained in a knowledge framework and automates the formulation of a valid stable, and preferably optimized, test for execution on an integrated circuit tester.

Method and apparatus for automated debug and optimization of in-circuit tests

A method and apparatus for maximizing the usage of a testhead of an in-circuit tester is presented. A testhead execution supervisor interfaces between a testhead controller and a graphical user interface used to enter manual tests. The testhead execution supervisor adds tests to be submitted to the testhead to one or more queues according to a priority scheme. Tests may be submitted to the testhead execution supervisor both as manual tests entered via the graphical user interface and as automatically generated tests generated by an automatic debug module. The automatic debug module may automatically generate tests for execution by the testhead that are executed when the testhead is idle, for example when no higher priority manual tests are scheduled.

Framework that maximizes the usage of testhead resources in in-circuit test system

A method for configuring an automated in-circuit test debugger is presented. The novel test debug and optimization configuration technique configures expert knowledge into a knowledge framework for use by an automated test debug and optimization system for automating the formulation of a valid stable in-circuit test for execution on an integrated circuit tester. In a system that includes a rule-based controller for controlling interaction between the test-head controller of an integrated circuit tester and an automated debug system, the invention includes a knowledge framework and a rule-based editor. The knowledge framework stores test knowledge in the representation of rules that represent a debugging strategy. The rule-based editor facilitates the use of rules as knowledge to debug or optimize an in-circuit test that is to be executed on the integrated circuit tester.

Method and apparatus for configuration of automated debug of in-circuit tests

A scheduling governor that regulates the number of scheduled tasks that are executed concurrently over a network computer system is presented. All task requests that are scheduled to be executed within a pre-specified interval of time, are serviced according to their priority. During heavy load times, the scheduling governor prevents overloads of the processing resources of the host computer by limiting the number of concurrently executing scheduled tasks to a pre-specified capacity dimension. Task requests that are unable to be run due to the governed cap on the number of allowed concurrently executing processes are given a priority to be executed once one of the fixed number of execution slots becomes available. Accordingly, the scheduling governor allows each scheduled task to be executed as close to its scheduled time as possible yet prevents system resource overload to improve efficiency and performance.

Thread based governor for time scheduled process execution

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Loveland, CO, United States of America

Roy H Williams