Sandisk 3d LLC

Matrix Semiconductor, Inc.

International Business Machines Corporation

Sandisk Technologies Inc.

Sandisk Corporation

Other

Silicon Valley Bank

Roy E Scheuerlein

Luca Giovanni Fasoli

Christopher John Petti

Alper Ilkbahar

Tyler J Thorp

Andrew J Walker

Tanmay Kumar

Bendik Kleveland

Tianhong Yan

George Samachisa

Sucheta Nallamothu

En-Hsing Chen

William Robert Reohr

Abhijit Bandyopadhyay

Nima Mokhlesi

James Montague Cleeves

Stephen McConnell Gates

S Brad Herner

Mark G Johnson

Matthew P Crowley

N Johan Knall

Deepak Chandra Sekar

Andrei Mihnea

Yung-Tin Chen

Xiying Costa

Christopher S Moore

Zhida Lan

J James Tringali

Feng Li

Xiaoyu Yang

Yoichiro Tanaka

Li Xiao

Brian Le

Chandrasekhar R Gorla

Albert T Meeks

Er-Xuan Ping

Stuart Stephen Papworth Parkin

Maitreyee Mahajani

Steven J Radigan

Ali K Al-Shamma

Derek Bosch

Thomas Yan

Douwe Johannes Monsma

Masaaki Higashitani

Randhir P Thakur

Peter Rabkin

Scott Brad Herner

Man Lung Mui

Klaus Florian Schuegraf

Gary Bela Bronner

Tong Zhang

William Joseph Gallagher

Henry Chien

Thomas H Lee

Tz-Yi Liu

Haibo Li

Yu Lu

Huiwen Xu

Perumal Ratnam

Kun Hou

Kedar Patel

Kenneth K So

David Russell Friedman

Seung Yu

Christopher Alan Moore

Colm P Lysaght

Yibo Nian

Igor Koutnetsov

Wendell P Noble

James K Kai

Seiki Ogura

Raul-Adrian Cernea

George Matamis

Chang Hua Siau

Vinod Robert Purayath

Takashi Whitney Orimoto

April Dawn Schricker

Raul Adrian Cernea

William Warren Walker

Chun-Ming Wang

Wing Kin Luk

Timothy Michael Kemp

James Harvey Kaufman

Stuart Stephen Parkin

Dietmar Gogl

Roger Hilsen Koch

John Davis Palmer

Roger March

Xiying Chen

Jingyan Zhang

Russell C Lange

James E Schneider

Pankaj Kalra

Daniel C Steere

Charles Timothy Ryan

Lucian A Kasprzak

Tao Du

Richard Matt Fruin

April D Shricker

Mark Clark

A nonvolatile memory device includes a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern. The nonvolatile memory cells may be pillar shaped non-volatile memory cells which can be patterned using triple or quadruple exposure lithography or by using a self-assembling layer.

Three dimensional hexagonal matrix memory array

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Three dimensional non-volatile storage with connected word lines

A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that a higher voltage is applied to anodes and a lower voltage to cathodes.

Low forming voltage non-volatile storage device

A method of programming a memory cell is provided. The memory cell includes a memory element having a first conductive material layer, a first dielectric material layer above the first conductive material layer, a second conductive material layer above the first dielectric material layer, a second dielectric material layer above the second conductive material layer, and a third conductive material layer above the second dielectric material layer. One or both of the first and second conductive material layers comprises a stack of a metal material layer and a highly doped semiconductor material layer. The memory cell has a first memory state upon fabrication corresponding to a first read current. The method includes applying a first programming pulse to the memory cell with a first current limit. The first programming pulse programs the memory cell to a second memory state that corresponds to a second read current greater than the first read current.

Dielectric-based memory cells having multi-level one-time programmable and bi-level rewriteable operating modes and methods of forming the same

Operating ReRAM memory is disclosed herein. The memory cells may be trained prior to initially programming them. The training may help to establish a percolation path. In some aspects, a transistor limits current of the memory cell when training and programming. A higher current limit is used during training, which conditions the memory cell for better programming. The non-memory may be operated in unipolar mode. The memory cells can store multiple bits per memory cell. A memory cell can be SET directly from its present state to one at least two data states away. A memory cell can be RESET directly to the state having the next highest resistance. Program conditions, such as pulse width and/or magnitude, may depend on the state to which the memory cell is being SET. A higher energy can be used for programming higher current states.

Method of operating FET low current 3D re-ram

A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes. A first set of pillar lines acts as local bit lines for accessing the memory elements together with an array of word lines on each plane. A second set of pillar lines is connected to the word lines. An array of metal lines on the substrate is switchable connected to the pillar lines to provide access to the first and second sets of pillar lines, thereby to provide access respectively to the bit lines and word lines of the three-dimensional array.

Method for non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines

A method is provided for programming a memory cell having a first terminal coupled to a word line and a second terminal coupled to a bit line. During a first predetermined time interval, the word line is switched from a first standby voltage to a first voltage, the bit line is switched from a second standby voltage to a predetermined voltage, and a voltage drop across the first and second terminals is a safe voltage that does not program the memory cell. During a second predetermined time interval, the word line is switched from the first voltage to a second voltage, and a voltage drop across the first and second terminals is a programming voltage that is sufficient to program the memory cell. Numerous other aspects are provided.

Methods and apparatus for reducing programming time of a memory cell

A three-dimensional array of memory elements reversibly change a level of electrical conductance/resistance in response to one or more voltage differences being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Local bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. Vertically oriented select devices are used to connect the local bit lines to global bit lines. A first subset of the vertically oriented select devices are positioned above the vertically oriented bit lines and a second subset of the vertically oriented select devices (interleaved with the first subset of the vertically oriented select devices) are positioned below the vertically oriented bit lines.

Three dimensional non-volatile storage with interleaved vertical select devices above and below vertical bit lines

Methods and apparatus for a solid state non-volatile storage sub-system of a computer is provided. The storage sub-system may include a write-many storage sub-system memory device including write-many memory cells, a write-once storage sub-system memory device including write-once memory cells, and a page-based interface that is adapted to read and write the write-once and write-many storage sub-system memory devices. Numerous other aspects are provided.

Storage sub-system for a computer comprising write-once memory devices and write-many memory devices and related method

A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements are each accessible by a word line in a plane and a local bit line. The three-dimensional array includes a two-dimensional array of pillar lines through the multiple layers of planes. The pillar lines are of a first type that act as local bit lines and a second type that provide access to the word lines by having respective memory elements preset to a permanently low resistance state for connecting second-type pillar lines for exclusive access to respective word lines. An array of metal lines on the substrate is switchably connected to the vertical bit lines to provide access to the local bit lines and the word lines.

Non-volatile 3D memory with cell-selectable word line decoding

A plurality of integrated circuit features are provided in the context of an array of memory cells including a plurality of word lines and a plurality of bit lines. Each memory cell includes a floating body or is volatile memory. The aforementioned features may include, among others, an option whereby the foregoing bit lines may be situated below a channel region of corresponding memory cells, etc.

Floating body memory cell system and method of manufacture

In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.

Multi-level memory arrays with memory cells that employ bipolar storage elements and methods of forming the same

A three-dimensional non-volatile memory system is disclosed including a memory array utilizing shared pillar structures for memory cell formation. A shared pillar structure includes two non-volatile storage elements. A first end surface of each pillar contacts one array line from a first set of array lines and a second end surface of each pillar contacts two array lines from a second set of array lines that is vertically separated from the first set of array lines. Each pillar includes a first subset of layers that are divided into portions for the individual storage elements in the pillar. Each pillar includes a second subset of layers that is shared between both non-volatile storage elements formed in the pillar. The individual storage elements each include a steering element and a state change element.

Three-dimensional memory structures having shared pillar memory cells

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Cupertino, CA, United States of America

Roy E Scheuerlein