Unisys Corporation

Roy E Greeff

Bruce H Williams

Glenn A Arbanas

Bruce Howard Williams

Mark B Falslev

A high speed bit synchronizer is provided with a digital phase detector and a digital offset eliminating circuit. The output of the digital offset eliminating circuit is summed together with the output of the digital phase detector to compensate for the DC offset voltage generated by unsymmetrical digital data received at the input of the phase detector. Further, the phase error offset voltage produced at the output of the digital phase detector is linearized so that the lock point of the phase S-curve located on a linearized portion of a phase offset S-curve, thus, substantially eliminating all seeking and jitter that normally occurs at the lock point.

Digital/analog bit synchronizer

An improved quadrature phase shift key modulator circuit of the type which includes a non-linear amplifier in the transmitter and includes a frequency select logic circuit for receiving the in phase and quadrature phase digital data to be modulated onto a carrier frequency signal. The output of the frequency select circuit produces select signals that are coupled to the input of a digital carrier frequency generator. The digital carrier frequency generator synthesizes and increases, decreases, or leaves unchanged the carrier frequency as a representation of the data occurring on the in phase and quadrature phase input lines. The output of the digital carrier frequency generator is smoothed and converted to an analog signal which has a constant vector power magnitude during phase change. The constant vector power when amplified in a non-linear amplifier of the transmitter is not susceptible to regeneration of side lobes of the carrier signal, thus, provides a more narrow bandwidth modulated carrier frequency signal.

Offset quadrature phase shift keyed modulation circuit

An improved phase locked indication circuit for a Costas QPSK carrier recovery loop comprises an inphase channel, a quadrature channel and phase error channel each connected to an input of a three input summing circuit through a diode square law multiplier and wherein the error channel signal is filtered by a low pass filter to smooth the signal before being applied to the negative input of the summing circuit to diminish false lock and not locked signals. The locked and not lock conditions are separated one from the other by a large signal to noise ratio.

Phase lock indicator circuit for a high frequency recovery loop

A bit synchronizing circuit is provided with both analog and digital devices in an enhanced bit synchronizing circuit system. There is provided a digital phase detector and a digital lock detector which are compatible with analog circuity. The output of the digital phase detector is coupled to an analog summing circuit having an output which is coupled to a low pass filter (LPF). The analog output of the LPF is coupled to the input of a voltage controlled oscillator (VCO) which produces a data rate clock. The output of the digital lock detector is coupled to an analog summing circuit having an output coupled to a low pass filter (LPF). The output of the LPF is coupled to a comparator for generating a lock indication signal output. The output of the comparator is also coupled to a sweep circuit which is coupled to an input of the voltage controlled oscillator for resolving frequency uncertainties in the bit synchronizing circuit.

Digitally implemented phase and lock indicators for a bit synchronizer

A dual loop phase locked circuit is disclosed in which a first loop includes a phase detector, a filter, and a VCO; as a second loop includes a sweep voltage generator, a compensation circuit, and the filter of the first loop. Due to the compensation circuit, the VCO accurately tracks a signal from the sweep voltage generator, even though the filter has an electrical parameter that drifts with time and/or age and/or component selection.

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Salt Lake City, UT, United States of America

Roy E Greeff