International Business Machines Corporation

Other

Infineon Technologies Ag

Infineon Technologies North America Corp.

Roy Charles Iggulden

Ronald G Filippi

Edward William Kiewra

Ping-Chuan Wang

Stefan Weber

Stefan J Weber

Mark Hoinkis

Lawrence Alfred Clevenger

Kenneth Parker Rodbell

Yun-Yu Wang

Kaushik Chanda

James J Demarest

Axel Christoph Brintzinger

Larry Clevenger

Rajiv V Joshi

Chandrasekhar Narayan

Jay William Strane

Werner Robl

Peter Weigand

Rainer Florian Schnabel

Florian Schnabel

Padraic C Shafer

Robert Van Den Berg

Christopher Adam Feild

Jeffrey P Gambino

Carl John Radens

Vincent James McGahay

Kwong Hon Wong

David M Dobuzinsky

Chao-Kun Hu

Lynne Marie Gignac

Horatio Seymour Wildman

Sven Schmidbauer

Maria Ronay

Herbert Palm

Thomas Goebel

Ronald Gene Filippi, Jr

Chenting Lin

Robert Daniel Edwards

Ishtiaq Ahsan

Stephen K Loh

Hans W Poetzlberger

Keith K H Wong

Michael M Iwatake

Donna Diane Miura

Jeffery L Hurd

Chet Dziobkowski

Kwong Hon (Keith) Wong

Ebrahim A Mehter

Edward W Kiewara

Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.

Post chemical mechanical polishing etch for improved time dependent dielectric breakdown reliability

Methods of forming a gas dielectric structure for a semiconductor structure by using a sacrificial layer. In particular, one embodiment of the invention includes forming an opening for semiconductor structure in a dielectric layer on a substrate; depositing a sacrificial layer over the opening; performing a directional etch on the sacrificial layer to form a sacrificial layer sidewall on the opening; depositing a conductive liner over the opening; depositing a metal in the opening; planarizing the metal and the conductive liner; removing the sacrificial layer sidewall to form a void; and depositing a cap layer over the void to form the gas dielectric structure. The invention is easily implemented in damascene wire formation processes, and improves structural stability.

Gas dielectric structure forming methods

In the back end of an integrated circuit employing dual-damascene interconnects, the interconnect members have a first non-conformal liner that has a thicker portion at the top of the trench level of the interconnect; and a conformal second liner that combines with the first liner to block diffusion of the metal fill material.

Method to improve time dependent dielectric breakdown

A method and structure for the detection of residual liner materials after polishing in a damascene processes includes an integrated circuit comprising a substrate; a dielectric layer over the substrate; a marker layer over the dielectric layer; a liner over the marker layer and dielectric layer; and a metal layer over the liner, wherein the marker layer comprises ultraviolet detectable material, which upon excitation by an ultraviolet ray signals an absence of the metal layer and the liner over the marker layer. Moreover, the marker layer comprises a separate layer from the dielectric layer. Additionally, the ultraviolet detectable material comprises fluorescent material or phosphorescent material.

Detection of residual liner materials after polishing in damascene process

Method of forming interconnect structure or interconnect and via structures using post chemical mechanical polishing

A method and apparatus for detecting metal extrusion associated with electromigration (EM) under high current density situations within an EM test line by measuring changes in capacitance associated with metal extrusion that occurs in the vicinity of the charge carrying surfaces of one or more capacitors situated in locations of close physical proximity to anticipated sites of metal extrusion on an EM test line are provided. The capacitance of each of the one or more capacitors is measured prior to and then during or after operation of the EM test line so as to detect capacitance changes indicating metal extrusion.

Capacitive monitors for detecting metal extrusion during electromigration

In a method of fabricating a metallization structure during formation of a microelectronic device, the improvement of reducing metal shorts in blanket metal deposition layers later subjected to reactive ion etching, comprising:

Low Cu percentages for reducing shorts in AlCu lines

A semiconductor device with openings of differing depths in a substrate or layer is described, as are related methods for its manufacture. Through selective deposition of a single mask layer, whereby low aspect ratio openings are substantially coated while high aspect ratio are at most partially coated, subsequent etching of the substrate or layer is restricted to uncoated portions of the high aspect ratio openings. The result is a substrate or layer with openings of more than one depth using a single mask layer. In a second embodiment, the selective deposition of a single mask layer is utilized to etch a layer while protecting underlying structures from etching. In a third embodiment, the selective deposition of a single mask layer is utilized to etch an opening into a layer wherein the opening has a sub-lithographic diameter, i.e., the diameter of the opening is smaller than can be achieved with the particular lithographic technique employed.

Etching openings of different depths using a single mask layer method and structure

A conductor for interconnecting integrated circuit components having improved reliability. The conductor includes a liner surrounding at least three surfaces of the conductor, producing a low textured conductor. It has been found that low textured conductor results in improved electromigration lifetime.

Device interconnection

A method of filling a damascene structure with liner and W characterized by improved resistance and resistance spread and adequate adhesion comprising: a given damascene structure coated by a liner which purposely provides poor step coverage into the afore mentioned structure, followed by a CVD W deposition, and followed by a metal isolation technique.

Liner with poor step coverage to improve contact resistance in W contacts

High aspect ratio vias formed in a first insulating layer covering a semiconductor substrate (body) are filled with conductors in a manner that both reduces the number of processing steps and allows an alignment tool (stepper) to align to alignment and overlay marks. Sidewalls and a bottom of each via are coated with a composite layer of titanium, titanium nitride, and a chemical vapor deposited seed layer of aluminum. A physical vapor deposited layer of aluminum is then formed while the structure is heated to about 400 degrees C. to completly fill the vias and to overfill same to form a blanket layer of aluminum above the first insulating layer ( ). The blanket layer of aluminum is then patterned and portions not covered by the pattern are removed to result in columns of aluminum. A second insulating layer is then formed around the columns of aluminum. The ends of the columns at a top of the second insulating layer lie in a relatively common plane to which steppers can relatively easily align patterns.

Semiconductor structure and method of fabrication including forming aluminum columns

A dual damascene process capable of reliably producing aluminum interconnects that exhibit improved electromigration characteristics over aluminum interconnects produced by conventional RIE techniques. In particular, the dual damascene process relies on a PVD-Ti/CVD-TiN barrier layer to produce aluminum lines that exhibit significantly reduced saturation resistance levels and/or suppressed electromigration, particularly in lines longer than 100 micrometers. The electromigration lifetime of the dual damascene aluminum line is strongly dependent on the materials and material fill process conditions. Significantly, deviations in materials and processing can result in electromigration lifetimes inferior to that achieved with aluminum RIE interconnects. In one example, current densities as high as 2.5 MA/cm are necessary to induce a statistically relevant number of fails due to electromigration.

Aluminum-based metallization exhibiting reduced electromigration and method therefor

A structure and process to define a via/interconnect structure is described. The structure is formed by reactive ion etching (RIE) where vias are formed first then the interconnects. The disclosed method relies on first depositing a metal with a thickness equivalent to the total height of the via and interconnect. Once vias are delineated by forming a hard mask and lithography, the lines are patterned using a lithographic step. Vias and lines are formed using lithography and RIE in one step and interfacial integrity is maintained resulting in high electromigration performance.

Dual-rie structure for via/line interconnections

Dual-RIE structure for via/line interconnections

A method of enriching the surface of a substrate with a solute material that was originally dissolved in the substrate material, to yield a uniform dispersion of the solute material at the substrate surface. The method generally entails the use of a solvent material that is more reactive than the solute material to a chosen reactive agent. The surface of the substrate is reacted with the reactive agent to preferentially form a reaction compound of the solvent material at the surface of the substrate. As the compound layer develops, the solute material segregates or diffuses out of the compound layer and into the underlying substrate, such that the region of the substrate nearest the compound layer becomes enriched with the solute material. At least a portion of the compound layer is then removed without removing the underlying enriched region of the substrate. For microcircuit applications, the method can be used to enrich the surface of an aluminum line with elemental copper to improve the electromigration resistance of the line.

Method of forming a solute-enriched layer in a substrate surface and article formed thereby

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Newburgh, NY, United States of America

Roy Charles Iggulden