Intel Corporation

Roy Callum

Patrick L Connor

Anshuman Thakur

Linden Minnick

Techniques to prevent interruption of operations performed by an I/O device. One advantage may be that the I/O device does not need to re-establish its interrupted operation (and waste the associated time to re-establish its interrupted operation). Accordingly, bus utilization efficiency may be improved.

Bus management techniques

The present disclosure describes a method comprising issuing a plurality of commands to a controller, wherein the commands are issued in a first order, and wherein the completion status of commands is written to the memory in a second order, and wherein the second order may be different from the first order. Also described is an apparatus comprising a controller adapted to accept a plurality of commands, wherein the commands are issued in a first order, and completion status of commands is written to the memory in a second order, and wherein the second order may be different from the first order.

Method for indicating completion status of asynchronous events

A system, protocol and related methods for providing secure manageability are generally described. In this regard, a communication protocol is introduced comprising an authentication protocol, responsive to an initialization event in a host device, to authenticate a remote device and establish an initial anti-replay value, and a secure communication protocol, selectively invoked upon authentication of the remote device, to facilitate subsequent communications between at least the host device and the authenticated remote device utilizing the initial anti-replay value in at least a first of said subsequent communications.

System, protocol and related methods for providing secure manageability

A method and apparatus for controlling access to a plurality of resources at a predetermined ratio based on multiple received requests. The system includes a series of multiplexors, adders, subtractors, multi-bit clocked registers, and comparators arranged to maintain the desired predetermined ratio. The registers act to maintain a first value correlated to a first quantity of requests granted for a first requester in excess of an amount desired according to the predetermined ratio and maintain a second value correlated to a second quantity of requests granted for a second requester with respect to the total requests desired from the second requester. One comparator compares the value from the first register with a predetermined value to assess whether to grant access to the first requestor.

Method and apparatus for statistically controlling priority between queues

One embodiment of a method may include partitioning data into segments of the data, storing in memory a set of checksums of the segments of the data, selecting a portion of the data, and determining a checksum of the portion of the data. The portion of the data may comprise a subset of the segments of the data and/or at least one part of at least one segment of the data. The checksum of the portion of the data may be determined, based, at least in part, upon a checksum of the subset of the segments and/or a checksum of the at least one part of the at least one segment. The checksum of the subset of the segments may be based, at least in part, upon respective checksums, read from the checksums stored in the memory, of segments of the data comprised in the subset of the segments.

Checksum determination

A circuit includes an operation unit adapted to perform a circuit operation in a plurality of rounds. The operation unit may operate properly under a predetermined range of operating conditions. The operation unit is adapted to select between receiving an input signal and a test signal and to perform a test round of the circuit operation when the test signal is selected. The circuit is adapted to compare a reference value with a result of the test round, the reference value identifying a correct value for the result of the test round when the operation unit is operating under the predetermined range of operating conditions. The operation unit is further adapted to receive a disable signal to disable the operation unit from performing the circuit operation when the result of the test round does not match the reference value. Other embodiments are described and claimed.

Method and apparatus to verify circuit operating conditions

A cryptographic accelerator for handling instruction-intensive bit permutations. The cryptographic accelerator comprises a selector and a plurality of buses coupled to the selector. Herein, at least one of the plurality of buses includes signal lines routed to perform a bit permutation operation incoming data. The bit permutation operation is one of a plurality of operations associated with a symmetric key function.

Cryptographic accelerator

A cryptographic packet processing unit performing cryptographic operations on a data portion of a data packet based on control information included in a header of the data packet. The cryptographic packet processing unit comprises a cryptographic bus interface unit, a crypto-processing unit, and a control storage unit. The cryptographic bus interface unit is capable of (i) receiving the data packet and (ii) removing the control information from the data portion. Coupled to the cryptographic bus interface unit, the crypto-processing unit is capable of performing a cryptographic operation on the data portion under the control of the control storage unit, which contains the control information.

Growing community of inventors

Beaverton, OR, United States of America

Roy Callum