Koninklijke Philips Corporation N.v.

Philips Electronics North America Corporation

Koninklijke Phillips Electronics N.v.

Roy Arthur Colclaser

James R Spehar

David M Szmyd

Guido Jozef Maria Dormans

Guoqiao Tao

Donald Robert Wolters

Neil Morris

There is a test structure on a semiconductor substrate for testing misalignment between adjacent implanted regions of opposite conductivity in a semiconductor device. In an example embodiment, the test structure includes a first and a second triple well structure; the second triple well structure is adjacent to the first triple well-structure in a first direction. Each structure includes a lower buried n-well region, a p-well region, a p-region, an n-well region and a base n-region, wherein a central base portion and a central n-well region portion are common to the first and the second structure, with the central base portion as a symmetry line with a width. Between the central base portion and the p-well region in the first triple well-structure a first overlay, and between the central base portion and the p-well region in the second triple well-structure a second overlay is provided.

Test structure for electrical well-to-well overlay

Non-volatile memory cells, high voltage transistors and logic transistors integrated on a single chip

The invention provides a way of protecting a differential pair of transistors by providing a current path between input terminals of the transistors, while limiting the voltage across reversed biased junctions of the transistors. The invention also allows a larger swing of input voltage at the input terminals of the transistors. According to the present invention, an electrostatic discharge protection circuit is provided for protecting a differential pair of transistors. Each transistor includes first and second terminals and an input terminal. The second terminals of the transistors are connected to each other. The circuit comprises a pair of bypassing circuits and a clamping circuit. Each bypassing circuit is connected in parallel with a junction formed by the input and second terminals of an associated one of the transistors to limit a voltage across the junction when the junction is reverse biased. The clamping circuit is connected in parallel with the two input terminals of the transistors for setting an allowed differential voltage swing between the input terminals to a predetermined level.

ESD protection devices for a differential pair of transistors

An ESD diode protects a circuit against electrostatic discharge (ESD). The ESD diode has four adjacent regions. The first and third regions are formed by doping a semiconductor substrate so that it has a P-type conductivity. The second and fourth regions are formed by doping the semiconductor substrate so that it has an N-type conductivity. The first region is for connection to a signal terminal of the circuit being protected when the fourth region is connected to a positive power line of the circuit. The fourth region is for connection to the signal terminal when the first region is connected to the ground line or a negative power line of the circuit.

ESD diode structure

A circuit arrangement provides a way of protecting a differential pair of bipolar transistors by diverting the current into an n-channel MOSFET which is driven into conduction during an ESD event and allows a larger swing of input voltage than the anti-parallel diode pair. No extra processing steps are required and the MOSFET is driven on, rather than relying on parasitic bipolar npn transistor triggering into snap-back as in the grounded gate NMOS transistor that is commonly used for ESD protection in CMOS integrated circuits. An ESD protection circuit is provided for protecting a differential pair of transistors having two input terminals. The circuit comprises a switching element (such as an NMOS transistor) having first and second terminals and a control terminal; a first resistive element, coupled between the first and control terminals of the switching element; and a second resistive element, coupled between the second and control terminals of the switching element; wherein the first and second terminals of the switching element are for connecting, respectively, to input terminals of the different pair.

ESD protection devices

A bi-directional ESD diode protects a circuit against electrostatic discharge (ESD). The bi-directional diode has a first device and a second device, each including a first region and a third region formed by doping a semiconductor substrate so that it has a P-type conductivity; and a second region and a fourth region formed by doping the semiconductor substrate so that it has an N-type conductivity. The first region of the first device and the fourth region of the second device are for connection to an anode terminal of the bi-directional diode. The fourth region of the first device and the first region of the second device are for connection a cathode terminal of the bi-directional diode. The anode terminal is for connection to a signal terminal of the circuit when the cathode terminal is connected to a positive power line of the circuit, and the cathode terminal is for connection to the signal terminal when the anode terminal is connected to a ground line or a negative power line of the circuit.

Bi-directional ESD diode structure

An integrated circuit includes electrostatic discharge (ESD) protection circuits coupled to protect I/O pins and or operational circuits from damage due to ESD events. The ESD protection circuits are coupled to fuses which in turn are coupled to external program pin(s) of the IC. The fuses can be opened via the external program pin(s) to substantially completely remove the capacitive loading on the I/O pins as well as any internal circuitry within the IC. The ESD circuits may protect against ESD damage during testing, packaging, shipping and installation into a system, and then be subsequently removed via the external program pins, such as upon first application of power to the IC via the system. Because fuses are used, the added capacitive loading of the deselection circuit is substantially zero and much less than active switching elements. The ESD deselection structure is beneficial for very high frequency RF circuits, where capacitive loading problems are particularly acute.

Growing community of inventors

Albuquerque, NM, United States of America

Roy Arthur Colclaser