Mellanox Technologies, Ltd.

Panaya Ltd.

Synopsys, Inc.

Roy Armoni

Or Davidi

Mati Cohen

Nurit Dor

Yossi Cohen

Dror Weiss

Naiyong Jin

Yael Meller

Dana Fisman Ofek

Embodiments are disclosed for solving a Boolean formula generated from an input design using an iterative loop using a computer-implemented Boolean satisfiability solver. An example method includes accessing data qualifier signals indicating one or more variables in a Boolean formula. The example method further includes marking the one or more variables in the Boolean formula as data qualifier variables based on the respective data qualifier signals. The example method further includes instructing a computer implemented Boolean satisfiability solver to solve the Boolean formula using an iterative loop, where operation of the iterative loop is prioritized based on the data qualifier variables. Corresponding apparatuses and non-transitory computer readable storage media are also provided.

Method and apparatus for improving Boolean satisfiability solver generated based on input design with data qualifier signals

An apparatus for IC design includes a memory configured to store an original Register Transfer Level (RTL) model, a corrected RTL model, and a translation of the original RTL model into a netlist. A processor is configured to identify in the original RTL model a flip-flop having a next-state function that is not equivalent to a corresponding next-state function of a corresponding flip-flop in the Corrected RTL model, to find a wire, which is the earliest ancestor of the flip-flop for which there is no equivalence between the original RTL model and the corrected RTL model, to check whether the wire has an equivalent net in the netlist, to identify, upon finding that the wire has no equivalent net, one or more ancestors of the wire, which do have equivalent nets in the netlist, and to modify the netlist to match the corrected RTL model.

Methods for automatic engineering change order (ECO) bug fixing in integrated circuit design

A method for circuit design automation includes receiving an initial RTL definition of a design of a circuit, and synthesizing an initial netlist of the circuit based on the initial RTL definition. After synthesizing the initial netlist, an updated RTL definition containing a design change and a corresponding updated netlist are received. The updated RTL definition and netlist are automatically analyzed to identify first and second logical relations that were changed in the RTL definition and netlist, respectively. A notification is issued of sets of the endpoints between which the first logical relations were changed without changes to the second logical relations or vice versa. For the sets of the endpoints between which both the first logical relations and the second logical relations were changed, the equivalence between the first and second logical relations is automatically verified.

Checking equivalence between changes made in a circuit definition language and changes in post-synthesis nets

A method, computer program, and apparatus are described for finding the logical equivalence between register transfer level (RTL) wires and post synthesis nets in a netlist. In some example embodiments, the method includes minimizing nets in a netlist and matching each RTL wire to a netlist net. In some example embodiments, the method also includes determining if an RTL wire is logically equivalent to a netlist net. In some example embodiments, the method also includes determining a new candidate for a net if the RTL wire and associated netlist net are not logically equivalent.

Method and apparatus for finding logic equivalence between register transfer level and post synthesis nets

A certain subset of temporal properties defined using local variables can be formally verified with complexity of PSPACE or less. A subset with this characteristic, referred to as a practical subset, is therefore feasible to formally verify. For example, it can be shown that temporal properties that possess an alternating automaton with no conflicts fall within a practical subset. Temporal properties are analyzed to determine whether they are a member of the practical subset. Members of the practical subset can then be feasibly formally verified.

Formal verification of temporal properties expressed using local variables

Methods for accessing impact analysis repositories and transaction-refinement index for each of the impact analysis repositories. According to the obtained transaction-refinement index, associating the combined repository with information from the most transaction refined impact analysis repository. Associating the combined repository with information from the less transaction refined impact analysis repository in the case of a request to insert or delete a table record for tables that do not contain any impacted transaction in the more transaction refined impact analysis repository. And associating the combined repository with information from the less transaction refined impact analysis repository in the case of a request to update a table record for table columns that do not contain any impacted transaction in the more transaction refined impact analysis repository.

Methods for calculating a combined impact analysis repository

One non-limiting embodiment of the invention comprises the steps of accessing at least two impact analysis repositories, calculating a combined impact analysis repository from the at least two impact analysis repositories, and utilizing the combined impact analysis repository for supplying better quality impact analysis results.

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Givat Ada, Israel

Roy Armoni