International Business Machines Corporation

Roy A Wood

George A Williams, Ii

John E Campbell

Robert R Livolsi

Robert James Lynch

Dennis T Cox

Charles H Milligan

William F Washburn

Steven F Hajek

Michael James Chan

Gilbert J Kelly

Frank A Almquist

Cyril A Price

Andrew M Simon

John F Larsen

Stephen W Flaherty

David F Anderson

Justin Bruce Damerell

A method and system are disclosed for selectively altering the functional characteristics of a data processing system without physical or mechanical manipulation. A data processing system is first manufactured having a predetermined set of functional characteristics. A multibit alterable code which includes a functional characteristic definition is then initially loaded into physically secure, nonvolatile memory within the data processing system, utilizing an existing bus, or a fusible link which may be opened after loading is complete. The functional characteristic definition is loaded from nonvolatile memory into a nonscannable register within a secure portion of a control logic circuit each time power is applied to the data processing system and the definition is then utilized to enable only selected functional characteristics. Alternate functional characteristics may thereafter be selectively enabled by entering a security code which matches one of a number of preloaded codes and an encoded alternate functional characteristic definition. The alternate functional characteristic definition may be enabled on a one-time, metered, or regularly scheduled basis and variable capability data processing systems may be implemented in this manner utilizing a single manufactured system, without the necessity of manufacturing and storing multiple data processing system models.

Method and system for selectively altering data processing system

Electrical characteristics of the inputs to VLSI semiconductor chips can be modified after the chips are fabricated and mounted into multichip modules (packages), at which time the required characteristics are known accurately. The changes are accomplished by incorporating special circuitry at the chip inputs during their design combined with the use of `boundary-scan` type circuitry that has recently been put in place for device testing. The circuitry allows the impedance characteristics of the chip's receiver to be modified to match that of the driving source and the wiring interconnections between the chip and source. The test circuitry is used to provide the logical signals to selectively switch the circuits to the proper configuration. This enables optimally designed interconnections between the input and output circuitry on the chips and thereby avoids the necessity for costly re-designs.

Logically configurable impedance matching input terminators for VLSI

This specification describes means that permit the variation of circuits, particularly latch circuits, used in programmable logic array chips (PLAs). The latch circuits are changeable to enable the selection of one of three different latch configurations to be used or in combination on the same PLA chip. The differences in the circuit configurations of the different types of latches occur only in metallization pattern of the chip so that chips with different latch configurations can be manufactured with a minimum of different processing steps.

Programmable latch and other circuits for logic arrays

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Saugerties, NY, United States of America

Roy A Wood