Rambus Inc.

Other

Roxanne T Vu

Benedict C Lau

Leung Yu

Huy M Nguyen

Donald C Stark

Kevin S Donnelly

Stefanos Sidiropoulos

Bruno Werner Garlepp

Jared L Zerbe

Mark A Horowitz

Jun Y Kim

Tsyr-Chyang Ho

Benedict Chung-Kwong Lau

Jade M Kizer

James A Gasbarro

Simon Li

Adam Chuen-Huei Chou

Huey M Nguyen

Craig Edward Hampel

Charles Walter Boecker

Eric Douglas Groen

Marko Aleksić

Carl William Werner

Pak Shing Chau

Clemenz L Portmann

Richelle L Smith

Kevin S Donelly

Jared Levan Zerbe

Horowitz Mark A A

Disclosed is a system where indicators of the relative phase differences between combinations of clocks in a multi-phase clock system are developed and/or measured. These indicators convey information regarding which phase difference between a given pair of the clocks is greater than (or less than) the phase difference between another pair of the clocks. This information is used to sort/rank/order phase differences between the various combinations of pairs of clocks according to their phase differences. This ranking is used to select the pair of clocks to be adjusted.

Adjustment of multi-phase clock system

The embodiments herein describe technologies of an amplifier circuit that is designed for wideband communication with superconductive components in cryogenic applications, including Josephson Junction integrated circuits, operating in a cryogenic temperature domain (e.g., 4K). The amplifier circuit operates in a temperature domain (e.g., 77K) that is higher than the cryogenic temperature domain of the superconductive components.

Amplifier circuit for cryogenic applications

A receiver with clock phase calibration is disclosed. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.

Phase calibration of clock signals

An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

Flash memory controller with calibrated data communication

A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.

Memory controller that calibrates a transmit timing offset

Memory system with calibrated data communication

Memory controller with circuitry to set memory device-specific reference voltages

A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device samples the data sequence to produce receiver data. The second device then transmits the receiver data back to the first device. Within the first integrated circuit device, a comparison between the data sequence and the receiver data is performed, and based on the comparison, the first device generates information representative of a calibrated timing offset. The first device uses the information representative of the calibrated timing offset to adjust timing associated with transferring write data from the first integrated circuit to the second integrated circuit.

Calibrated data communication system and method

A system and method for configuring a receiver such that the duty cycle of the receiver clock accurately matches the duty cycle of the data signal received. This adaptive system and method calibrates a receiver's duty cycle to optimize the receiver timing margin for different data signal types and different slave devices. In one embodiment, a duty cycle correction circuit matches the receiver clock to a predetermined duty cycle. The receiver clock is then configured to have a duty cycle skewed from the predetermined duty cycle based on the specific data signal received. In a receiver system utilizing a clock tree, individual branches of the clock tree are configured to have respective duty cycles skewed to match the duty cycle of a data signal received from a specific transmitting device.

System and method for adaptive duty cycle optimization

Growing community of inventors

San Jose, CA, United States of America

Roxanne T Vu