Nvidia Corporation

Other

Rouslan Lyubomirov Dimitrov

Sau Yan Keith Li

Lars Nordskog

Emmett Michael Kilgariff

Allison Phuong Huynh

Ziyad Sami Hakura

Dale L Kirkland

Eric Brian Lum

Yury Y Uralsky

Viktor Grigoryevich Vandanov

Chris Amsinck

Lacky V Shah

Walter E Donovan

Rui Manuel Bastos

Sachin Satish Idgunji

Thomas A Petersen

Andrei Khodakovsky

Ankan Banerjee

Scott Phillip Cutler

Siddharth Sharma

Shishir Goyal

Jerome Francis Duluk, Jr

Gerrit Ary Slavenburg

Wishwesh Anil Gandhi

Santanu Dutta

Olivier Lapicque

Lei Yang

James Howard

Seth P Schneider

Kirill A Dmitriev

Cody J Robson

Tzyywei Hwang

David Wyatt

Jack H Choquette

Shirish C Gadre

Albert Meixner

Karim Abdalla

Rui Bastos

Thomas Francis Fox

Tom J Verbeure

Ross Cunniff

Karan Mehra

Omkar Paranjape

Robert Jan Schutten

Morgan Samuel McGuire

Gentaro Hirota

Walter Robert Steiner

Josef Bo Spjut

Charles N Hansen

Tony Tamasi

Cynthia Ann Edgeworth Allison

Gregory Scott Palmer

Joohwan Kim

Louis Bavoil

Praveen Krishnamurthy

Miguel Sainz

Cynthia Allison

Patrick James Neill

David Matthew Stears

Jeff Pool

Dmitriy Zhdan

Benjamin Boudaoud

Pierre Souillot

Rajballav Dash

Ignacio Llamas Ubieto

Seth Schneider

Jensen Huang

Laurence Harrison

Ajay Kamalvanshi

Sriharsha Niverty

Dmitry Zhdan

Cody Robson

Milton Lei

Charles Hansen

Tom Petersen

Paul Van Der Kouwe

Robert Osborne

A weighted average execution time associated with each execution stage of a plurality of execution stages used to process a plurality of frames in parallel is obtained. The processing of each of the plurality of frames is performed at each of the plurality of execution stages in a sequential order, starting with an initial execution stage and continuing with each subsequent execution stage. A first largest weighted average execution time associated with one of the plurality of execution stages is determined. A delay to the initial execution stage prior to processing a first next frame is applied. The delay is determined based on the first largest weighted average execution time.

Dynamically reducing latency in processing pipelines

A blended reality user interface and gesture control system includes one or more sensors, a head-mounted display, and a blending engine. The blending engine is configured to receive a live reality and virtual reality feeds, track movement of a user using the sensors, detect a command based on the tracked movement, blend the live and virtual reality feeds into a blended view based on the detected command, and display the blended view on the head-mounted display. In some embodiments, the blending engine is further configured to detect an amount of head tilt of the user and adjust a blending factor controlling an amount of transparency of the live reality feed within the blended view based on the amount of head tilt. In some embodiments, the blending engine is further configured to detect manipulation of a controller by the user and adjust the blending factor based on the detected manipulation.

System and method for a blended reality user interface and gesture control system

A performance metrics of a receiver is obtained using frames of an application hosted by a server that are received via a network. The one or more performance metrics include information indicative of a current occupancy of a frame buffer corresponding to the receiver and information indicative of a target occupancy of the frame buffer corresponding to the receiver. The frame buffer of the receiver is used to queue frames of the application for display. A frame rate associated with rendering at least one next frame of the application is adjusted using the one or more performance metrics of the receiver to control population of the frame buffer. Subsequent frames of the application hosted by the server are rendered using the adjusted frame rate. Upon rendering the subsequent frames, the server sends the subsequent frames to the receiver for display.

Dynamically reducing stutter and latency in video streaming applications

Embodiments of the present invention provide end-to-end frame time synchronization designed to improve smoothness for displaying images of 3D applications, such as PC gaming applications. Traditionally, an application that renders 3D graphics functions based on the assumption that the average render time will be used as the animation time for a given frame. When this condition is not met, and the render time for a frame does not match the average render time of prior frames, the frames are not captured or displayed at a consistent rate. This invention enables feedback to be provided to the rendering application for adjusting the animation times used to produce new frames, and a post-render queue is used to store completed frames for mitigating stutter and hitches. Flip control is used to sync the display of a rendered frame with the animation time used to generate the frame, thereby producing a smooth, consistent image.

Systems and methods for frame time smoothing based on modified animation advancement and use of post render queues

Graphics processing unit (GPU) performance and power efficiency is improved using machine learning to tune operating parameters based on performance monitor values and application information. Performance monitor values are processed using machine learning techniques to generate model parameters, which are used by a control unit within the GPU to provide real-time updates to the operating parameters. In one embodiment, a neural network processes the performance monitor values to generate operating parameters in real-time.

Real-time hardware-assisted GPU tuning using machine learning

A display device for measuring the end-to-end latency of a computing system. The computing system includes an input device, a computing device, and the display device. The display device is directly connected with the input device and receives input data packets generated by the input device in response to received user input events. The display device passes the input packets to the computing device for graphics processing. The display device measures the end-to-end latency comprising the sum of three latencies. A first latency comprises an input delay of the input device. A second latency comprises an amount of time between generation of the input packet and a corresponding change in pixel values caused by the input event at the display device. A third latency comprises a display latency. The display device also displays latency information associated with the measured end-to-end latency.

System-latency-aware display device

The present disclosure is directed to a method and system for increasing virtual machine (VM) density on a server system through adaptive rendering by dynamically shifting video rendering tasks to a client computing device. In one embodiment, a processor in a server manages virtual machines in the server by controlling a number of VMs and an amount of system resources allocated to the VMs. The number of VMs and the amount of resources allocated to the VMs are controlled by shifting video rendering from at least one of the VMs to a client device, and increasing the number of the VMs in the server after the shifting.

Managing virtual machine density by controlling server resource

A parallel processing unit (e.g., a GPU), in some examples, includes a hardware scheduler and hardware arbiter that launch graphics and compute work for simultaneous execution on a SIMD/SIMT processing unit. Each processing unit (e.g., a streaming multiprocessor) of the parallel processing unit operates in a graphics-greedy mode or a compute-greedy mode at respective times. The hardware arbiter, in response to a result of a comparison of at least one monitored performance or utilization metric to a user-configured threshold, can selectively cause the processing unit to run one or more compute work items from a compute queue when the processing unit is operating in the graphics-greedy mode, and cause the processing unit to run one or more graphics work items from a graphics queue when the processing unit is operating in the compute-greedy mode. Associated methods and systems are also described.

Simultaneous compute and graphics scheduling

A tile-based system for processing graphics data. The tile based system includes a first screen-space pipeline, a cache unit, and a first tiling unit. The first tiling unit is configured to transmit a first set of primitives that overlap a first cache tile and a first prefetch command to the first screen-space pipeline for processing, and transmit a second set of primitives that overlap a second cache tile to the first screen-space pipeline for processing. The first prefetch command is configured to cause the cache unit to fetch data associated with the second cache tile from an external memory unit. The first tiling unit may also be configured to transmit a first flush command to the screen-space pipeline for processing with the first set of primitives. The first flush command is configured to cause the cache unit to flush data associated with the first cache tile.

Scheduling cache traffic in a tile-based architecture

Growing community of inventors

Santa Clara, CA, United States of America

Rouslan Lyubomirov Dimitrov