Freescale Semiconductor,inc.

Rounak Roy

Chetan Verma

Amit Roy

Vijay Tayal

Kushagra Khorwal

A method and system for reducing power consumption of an integrated circuit with an EDA tool by analyzing and modifying a layout design having a plurality of nets across multiple metal layers. The method includes identifying long nets in the layout design, determining an interconnect capacitance of each of the long nets, determining a net level switching activity of each of the long nets, generating a high power impact list using the interconnect capacitance and the switching activity of each of the long nets, modifying a metal spacing of the long nets listed in the high power impact list.

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Noida, India

Rounak Roy