Exar Corporation

Sierra Semiconductor

Netlogic Microsystems, Inc

Other

Roubik Gregorian

Bahram Fotouhi

Gaurav Malhotra

Shih-Chung Fan

Jyn-Bang Shyu

Mir Bahram Ghaderi

Vincent S Tso

Shin Chung Chen

Saied Rafati

Joseph N Babanezhad

Manop Thamsirianunt

Earl Gibson

A method and system are described for canceling an echo signal with an echo canceller in the analog domain. In one embodiment, a system includes an echo canceller that includes an interpolation unit, operating in a digital domain, that receives a first digital echo estimate signal from an LMS unit and generates a second digital echo estimate signal without oversampling. A digital-to-analog converter (DAC) receives the second digital echo estimate signal and generates an analog echo estimate signal without oversampling. The echo canceller prevents the DAC from adding a high frequency component to the analog echo estimate signal. A subtractor adds the analog echo signal to an incoming signal having an echo signal. The subtractor generates an analog signal with reduced echo signal in the useful frequency band of the incoming signal.

Analog echo canceller with interpolating output

A method and system are described for canceling an echo signal in analog domain with adaptive filters working in digital domain. In one embodiment, a system includes an analog-to-digital converter (ADC) sampling at two different phases to generate a first error signal and a second error signal having different phases. The ADC operates at a frequency significantly lower than the frequency at which the individual filters run. The first adaptive filter unit and a second adaptive filter unit are independently trained with the first and second error signals, respectively. The first and second adaptive filter units generate echo estimate signals used to cancel the echo signal.

Analog echo canceller with filter banks

A method and system are described for canceling an echo signal with an echo canceller in the analog domain. In one embodiment, a system includes an echo canceller that includes an interpolation filter unit, operating in a digital domain, that receives a first digital echo estimate signal from a LMS unit and generates a second digital echo estimate signal without oversampling. A digital-to-analog converter (DAC) receives the second digital echo estimate signal and generates an analog echo estimate signal without oversampling. The echo canceller prevents the DAC from adding a high frequency component to the analog echo estimate signal. A subtractor adds the analog echo estimate signal to an incoming signal having an echo signal. The subtractor generates an analog signal with reduced echo signal in the useful frequency band of the incoming signal.

A mechanism for dealing with faster clock speeds by increasing the pulse width of the pump-up and pump-down pulses of a Hogge-type phase detector without dividing the clock. In particular, the NRZ data stream is divided into two, interleaved data streams which are provided through two series of flip-flops. By connecting the exclusive-OR gates separately to the two series of flip-flops to generate the pump-up and pump-down pulses, a longer time between transitions can be achieved by having alternate transitions (up and down) used by the two different series of flip-flops. In addition, delay circuits are provided to compensate for the clock-to-data output delay of the flip-flops.

Interleaved pulse-extended phase detector

A technique for minimizing the effect of parasitic capacitance in a resistive gain amplifier. Instead of the resistors being formed directly over the substrate, or over an oxide of the substrate, a semiconductor element (e.g., an n-well) is used between the resistor and the substrate. For resistors in the input circuit, this semiconductor element is connected to the voltage input rather than ground. For the resistors in the feedback loop circuit, the semiconductor element is connected to the voltage output of the operational amplifier. The insertion of this semiconductor element provides the ability to programmably connect the parasitic capacitance to somewhere other than ground. By connecting the parasitic capacitance to the voltage input or voltage output, the ground connection is eliminated, eliminating the pole introduced by the parasitic capacitance.

Frequency compensation of wide-band resistive gain amplifier

A clock recovery circuit which has a transition detector connected to the incoming data stream. An output of the transition detector is connected to a gate, such as a D flip-flop, which has an input receiving the recovered clock. A zero or one output will be generated depending upon whether the transition is before or after the rising edge of the recovered clock. An accumulator circuit accumulates a count for each transition, providing the results to a comparison circuit. The comparison circuit compares the accumulated count to maximum and minimum thresholds, and provides advance or retard outputs when those thresholds are exceeded. A phase circuit adjusts the phase of the recovered clock by advancing or retarding it after a sufficient number of transitions have been detected either in advance or behind the recovered clock to justify such an adjustment.

Clock recovery circuit

A method and apparatus for automatically determining the protocol being used from the frequency of an applied clock without the need for a separate pin or switch or a second external clock. The clock's frequency is identified when its frequency falls into the set range for which the apparatus is targeted. Based on the detected frequency in the set range, a mode select signal is generated. The mode select signal causes the chip to configure to the appropriate frequency for that mode, as well as any other unique configuration parameters. In one embodiment, the invention generates a ramp signal triggered by the external clock (which is the clock frequency for the desired protocol). The clock is simultaneously applied to a counter. When the ramp signal reaches a reference voltage, the count of the counter is compared to at least one threshold to determine to which frequency it corresponds. In response to this determination, the chip is configured according to the communication mode or protocol indicated. This may be simply the appropriate frequency, but, depending upon the chip, may include pulse shaping, framing and other configuration selections.

Automatic frequency rate switch

A phase detector which detects the phase difference between the input clock and an output clock. That phase difference is used to gate a high frequency clock, which is provided to the clock input of an up/down counter. The phase detector also indicates whether the phase difference is positive or negative. When the counter reaches a pre-specified up or down count, an advance or retard signal is provided to a phase selector. The phase selector selects one of multiple phases of a clock used for the output clock.

Digital jitter attenuator using an accumulated count of phase differences

A phase detector which detects the phase difference between the input clock and an output clock. That phase difference is used to gate a high frequency clock, which is provided to an integration circuit. The phase detector also indicates whether the phase difference is positive or negative. The output of the integration circuit is provided to a comparator, which compares the value to a threshold. When the threshold is exceeded, an advance or retard signal is provided to a phase selector. The phase selector selects one of multiple phases of a clock used for the output clock.

Second order digital jitter attenuator

A voltage regulated charge pump is disclosed which is capable of regulating its output voltage without radiating switching noise or consuming more power than is necessary to maintain the output at its targeted level. The voltage regulated charge pump circuit and its method of regulation, according to the present invention, can reliably drive transmission lines in networking system and communication applications.

Voltage regulated charge pump

An operational amplifier that exhibits a relatively constant gain over process and temperature variations. The operational amplifier according to the present invention is designed such that its gain does not depend on process sensitive parameters such as mobility of field effect transistors.

Constant gain amplifier

A slew-rate limited output driver circuit that minimizes switching current while delivering sufficient peak load currents is disclosed. The circuit of the present invention includes fixed pull-up and pull-down transistors that are designed to dissipate minimum switching current while maintaining a predetermined slew rate. Additional pull-up and pull-down transistors are then switched in parallel to the fixed pull-up and pull-down transistors to drive the output all the way to full logic levels, after the output signal has made most of its transition. In a preferred embodiment, each switched transistor is controlled by a comparator that generates its output by comparing the level of the output signal to a predetermined reference voltage.

Slew rate limited output driver

A charge pump circuit that is capable of generating a voltage that is greater in absolute magnitude than that of the substrate voltage Vsub in circuits where the substrate cannot be pumped to a voltage that is greater in absolute magnitude than Vsub is disclosed. Various innovative circuit techniques are used to implement a, for example, negative charge pump circuit in an N-well CMOS process with all PMOS transistors. The negative charge pump circuit according to the present invention can reliably drive on-chip transmission line termination switches.

Negative charge pump circuit

Power dissipation is reduced in a video DAC by providing a sleep mode in which DAC current sources are shut off during the blanking period in a manner that allows them to be rapidly turned back on at the end of sleep mode. In particular, a digital to analog converter includes a current source for producing a current, a current steering circuit connected to the current source, the current steering circuit including switches responsive to first and second control signals, respectively, for steering the current into either a load or a current return path, and a control circuit for generating the first and second signals each as a logical combination of a video data signal and a sleep signal. The sleep signal, when it is active, causes both the first and second switches to turn off, which in turn causes the current source to turn off. In a preferred embodiment, the switches are MOSFETS having low gate capacitance. At the end of sleep mode, the current source may be rapidly turned back on by turning on one of the MOSFETS. Performance of the video DAC is therefore not affected, while power dissipation is substantially reduced, facilitating higher-level integration and compliance with the Green PC standard. Reduced power dissipation also allows for use of an inexpensive chip package, reducing manufacturing cost, and increases reliability of the chip.

Dynamic power saving video DAC

A circuit technique to achieve 14-bit resolution in a charge-redistribution CMOS analog-to-digital converter. The sign bit plus the six most significant bits are obtained using a 6-bit capacitor array, the next five bits are determined using a resistor array, and finally the last two bits are obtained by use of a second 2-bit capacitor array. The area of the resulting 14-bit A/D converter is not appreciably larger than a corresponding 12-bit A/D converter. The 6-bit capacitor array is realized by connecting unit capacitors of a unit capacitor array. In the second capacitor array, at least one of the capacitors is realized by subdividing the unit capacitor. Since the accuracy of capacitors in the second capacitor array need not be as great as the accuracy of capacitors in the 6-bit capacitor array, subdividing the unit capacitor does not affect the accuracy of the converter.

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Saratoga, CA, United States of America

Roubik Gregorian