Infineon Technologies Ag

Roswitha Deppe

Thomas Kuenemund

Georg Georgakos

Erwin Ruderer

Walther Lutz

Anton Huber

Sascha Siegler

A device includes a flip flop and a control circuit. The flip flop includes a flip flop data input terminal and a flip flop clock input terminal. The control circuit includes a control circuit data input terminal and a control circuit clock input terminal. The control circuit is configured to route, in a Data Processing Mode of the device, an incoming data signal from the control circuit data input terminal to the flip flop data input terminal and an incoming clock signal from the control circuit clock input terminal to the flip flop clock input terminal and to apply, in a Data Retention Mode of the device, a first given fixed signal value to the flip flop data input terminal independent of a value of the incoming data signal and a second given fixed signal value to the flip flop clock input terminal independent of a value of the incoming clock signal.

Device with a data retention mode and a data processing mode

Implementations are presented herein that relate to a standard cell including a measuring structure for controlling process parameters during manufacture of an integrated circuit. A standard cell is formed in a plurality of material layers of an integrated circuit to perform part of a function of the integrated circuit, wherein the plurality of material layers is configured to be patterned by a plurality of mask layers during manufacture of the integrated circuit, wherein the standard cell includes a measuring structure that is placed within boundaries of the standard cell, wherein the measuring structure includes at least one feature in at least one of the plurality of material layers and the plurality of mask layers, wherein the at least one feature is configured to provide measurement results in order to control process parameters during manufacture of one of the material layers and mask layers.

Measurement structure in a standard cell for controlling process parameters during manufacturing of an integrated circuit

In a method for designing integrated circuits comprising replacement logic components, a plurality of logic cells and a plurality of filler cells which fill interspaces between the logic cells are positioned on a chip area. In this case, some or all of the filler cells represent replacement logic components for the integrated circuit and have been or are interconnected or wired in such a way that they form capacitances in the integrated circuit.

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Munich, Germany

Roswitha Deppe