United States of America As Represented by the Secretary of the Air Force

Other

Ross W Dettmer

Tony K Quach

John L Ebel

Kenichi Nakano

James K Gillespie

James S Sewell

Christopher A Bozada

G David Via

Charles K Havasy

Gregory C DeSalvo

Thomas J Jenkins

Carl I Pettiford

Charles L Cerny

Charles L A Cerny

Gregory C Desalvo

An integrated circuit substrate via-hole fabrication arrangement providing for accurate determination of via-hole size and via-hole registration through use of a calibrated pattern formed into the integrated circuit substrate during portions of the normal circuit fabrication process. Initiation of the via-hole and fabrication of the calibrated pattern from one surface, such as the front side, of the integrated circuit wafer and completion of the via-hole from the opposite surface of the wafer are contemplated. The calibrated pattern may be one of several possible physical configurations and of selected dimensions usable with the process, materials and circuitry of the device being fabricated. Use of the invention in fabricating ground conductor-connected via conductors for gigahertz radio frequency-capable integrated circuits of the monolithic or mixed hybrid with monolithic type and having a ground plane element is contemplated.

Measured via-hole etching

An enhancement mode periodic table group III-IV semiconductor field-effect transistor complementary pair device is disclosed. The disclosed complementary pair include single metallization for ohmic and Schottky barrier contacts, a permanent non photosensitive passivation layer (a layer which has also been used for masking purposes during fabrication of the device) and gate elements of small dimension and shaped cross section to provide desirable microwave spectrum electrical characteristics. The complementary pair of the invention is fabricated from undoped semiconductor materials disposed in a layered wafer structure and selectively doped by ion implantation to achieve both the p-channel and n-channel transistors. The semiconductor materials may include two, one or zero buffer layers in their layer structure. The disclosed complementary pair is of reduced fabrication cost, increased dimensional accuracy and state of the art electrical performance.

Complementary heterostructure integrated single metal transistor apparatus

A method for fabricating a periodic table group III-IV metal semiconductor metal field-effect enhancement mode complementary transistor pair device is described, a device typically made of gallium arsenide materials. The disclosed fabrication uses initially undoped semiconductor materials, single metallization for ohmic and Schottky barrier contacts, employs a non-alloyed ohmic contact semiconductor layer and includes an inorganic dielectric material layer providing non photosensitive masking at plural points in the fabrication sequence. The invention uses selective ion implantations, and a combined optical and electron beam lithographic process, the latter in small dimension gate areas. These attributes are combined to provide a field-effect transistor complementary pair of reduced fabrication cost, low electrical energy operating requirements increased dimensional accuracy and current state of the art electrical performance. Fabricated device characteristics are also disclosed.

Complementary heterostructure integrated single metal transistor fabrication method

An enhancement mode periodic table group III-IV semiconductor field-effect transistor device is disclosed. The disclosed transistor includes single metallization for ohmic and Schottky barrier contacts, a permanent non photosensitive passivation layer (a layer which has also been used for masking purposes during fabrication of the transistor) and a gate element of small dimension and shaped cross section as needed to provide desirable microwave spectrum electrical characteristics. The transistor of the invention is fabricated from undoped semiconductor materials disposed in a layered wafer structure and selectively doped by ion implantation to achieve either a p-channel or an n-channel transistor. The semiconductor materials may include two, one or zero buffer layers in their layer structure. The disclosed transistor is of reduced fabrication cost, increased dimensional accuracy and state of the art electrical performance.

Single layer integrated metal enhancement mode field-effect transistor

A method for fabricating an enhancement mode periodic table group III-IV metal semiconductor metal field-effect transistor is described. The disclosed fabrication arrangement uses single metallization for ohmic and Schottky barrier contacts, employs initially undoped semiconductor materials--materials selectively doped in a disclosed processing step, employs a non-alloyed ohmic contact semiconductor layer and includes an inorganic dielectric material layer providing non photosensitive masking at plural points in the fabrication sequence along with permanent surface passivation. The invention uses a combined optical and electron beam lithographic process, the latter in small dimension gate areas. These attributes are combined to provide a field-effect transistor capable of microwave frequency use, of reduced fabrication cost, low electrical energy operating requirements increased dimensional accuracy and state of the art electrical performance. Fabricated device characteristics are also disclosed.

Single layer integrated metal process for enhancement mode field-effect

A room temperature wet chemical digital etching technique for, gallium arsenide or other semiconductor material. Hydrogen peroxide and an acid are used in a two step etching cycle to remove the gallium arsenide in approximately 15 .ANG. limited increments. In the first step of the cycle, gallium arsenide is oxidized by, for example, 30% hydrogen peroxide to form an oxide layer that is diffusion limited to a thickness of, for example, 14-17 .ANG. for time periods from 15 seconds to 120 seconds. The second step of the cycle removes this oxide layer with an acid that does not attack unoxidized gallium arsenide. These steps are repeated in succession using new reactant materials and cleaning after each reactant (to prevent reactant contamination) until the desired etch depth is obtained. Experimental results are presented demonstrating the etch rate and process invariability with respect to hydrogen peroxide and acid exposure times. A method for using a Hall effect measurement to determine the achieved change in surface layer thickness of doped semiconductor material is also included.

Digital wet etching of semiconductor materials

A method for fabricating a periodic table group III-IV HEMT/pHEMT field-effect transistor device. The disclosed fabrication arrangement uses a single metalization for ohmic and Schottky barrier contacts, employs selective etching with a permanent etch stop layer, employs a non-alloyed ohmic contact semiconductor layer and includes a permanent non-photosensitive secondary mask element. The invention includes provisions for both an all optical lithographic process and a combined optical and electron beam lithographic process These concepts are combined to provide a field-effect transistor device of reduced fabrication cost, increased dimensional accuracy and state of the art electrical performance.

Single layer integrated metal process for high electron mobility

A method for fabricating a periodic table group III-IV field-effect transistor device is described. The disclosed fabrication arrangement uses a single metallization for ohmic and Schottky barrier contacts, employs selective etching with a permanent etch stop layer, employs a non-alloyed ohmic contact semiconductor layer and includes a permanent semiconductor material secondary mask element, a mask element which can be grown epitaxially during wafer fabrication. The invention includes provisions for both an all optical lithographic process and a combined optical and electron beam lithographic process These concepts are combined to provide a field-effect transistor device of reduced fabrication cost, increased dimensional accuracy and state of the art electrical performance.

Field effect transistor process with semiconductor mask, single layer

A method for fabricating a periodic table group III-IV metal semiconductor metal field-effect transistor device is described. The disclosed fabrication arrangement uses a single metalization for ohmic and Schottky barrier contacts, employs selective etching with a permanent etch stop layer, employs a non-alloyed ohmic contact semiconductor layer and includes a permanent non photosensitive secondary mask element. The invention includes provisions for both an all optical lithographic process and a combined optical and electron beam lithographic process. These concepts are combined to provide a field-effect transistor device of reduced fabrication cost, increased dimensional accuracy and state-of-the-art electrical performance.

Single layer integrated metal process for metal semiconductor field

A periodic table group III-IV metal semiconductor metal field-effect transistor device is described. The disclosed device includes single metalization for ohmic and Schottky barrier contacts, an elective permanent etch stop layer, a non-alloyed ohmic contact semiconductor layer and a permanent non photosensitive secondary mask element. The invention may be achieved with one of an all optical lithographic process and a combined optical and electron beam lithographic process The disclosed field-effect transistor device is of reduced fabrication cost, increased dimensional accuracy and state of the art electrical performance.

Metal semiconductor field effect transistor (MESFET) device with single

A periodic table group III-IV field-effect transistor device is described. The disclosed device uses a single metalization for ohmic and Schottky barrier contacts, permanent plural etch stop layers, employs a non-alloyed ohmic connection semiconductor layer and includes a permanent semiconductor material-comprised secondary mask element, a mask element which can be grown epitaxially during wafer fabrication to perform useful functions in both the device processing and device utilization environments. The device of the invention may be achieved with both an all optical lithographic process and a combined optical and electron beam lithographic process The disclosed device provides a field-effect transistor of reduced fabrication cost, increased dimensional accuracy and state of the art electrical performance.

Field effect transistor device with single layer integrated metal and

A periodic table group III-IV HEMT/PHEMT field-effect transistor device and its fabrication is described. The disclosed fabrication arrangement uses a single metallization for ohmic and Schottky barrier contacts, employs selective etching with a permanent etch stop layer, employs a non-alloyed ohmic contact semiconductor layer and includes a permanent non photoresponsive secondary mask element affording several practical advantages during fabrication and in the completed transistor. The invention includes provisions for both an all-optical lithographic fabrication process and a combined optical and electron beam lithographic process. These concepts are combined to provide a field-effect transistor device of reduced fabrication cost, increased dimensional accuracy and state of the art electrical performance.

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Dayton, OH, United States of America

Ross W Dettmer