Hewlett-packard Company

Ross V La Fetra

John F Shelton

Lee O Fleming

A fast cache hit detection method and apparatus. The present invention provides a method and apparatus for quickly determining whether there is a cache hit in cache memory systems utilizing error corrected tags. The hit detection process is split into two paths. The first path includes a circuit to check and correct a tag stored in the cache memory. The second path tests the validity of the tag stored in the cache memory by computing the appropriate ECC information using memory address information supplied by the computer CPU and comparing the tag and ECC stored in the cache memory to the CPU address and computed ECC. As the computed ECC is performed in parallel with the cache RAM access, this second path provides hit confirmation faster than the first path which must process the tag and ECC stored in the cache RAM through a ECC check and correction circuit. If a fast hit is confirmed, then the cache memory system can proceed to supply cache data to the CPU. If a fast hit is not confirmed, then the cache memory system waits for the first path to check and correct, if required, the tag stored in the cache and then test the corrected tag. As the cache tag typically does not need correction and most cache systems have a high hit rate, this invention dramatically increases the efficiency of the cache memory system.

Fast comparison method and apparatus for error corrected cache tags

A computing system includes a processor, a system memory containing data utilized by the processor and two cache memories. Each cache memory is connected directly to the processor. A first cache memory is connected to the processor and to the system memory. The first cache memory contains a subset of data in the system memory. A second cache memory is also connected to the processor. The second cache memory contains a subset of data in the first cache memory. Data integrity in the system memory is maintained using the first cache memory only. Whenever the processor writes data, the processor writes data both to the first cache memory and to the second cache memory. Whenever the processor reads data, the processor attempts to read data from the second cache memory. If there is a miss at the second cache memory, the processor attempts to read data from the first cache memory. If there is a miss at the first cache memory, the data is retrieved from the system memory and placed in the first cache memory. The processor then reads the data from the first cache memory. Generally, when the processor reads data from the first cache memory, the read data is written into the second cache memory.

Computing system with a cache memory and an additional look-aside cache

An improved integrated circuit chip design which is better adapted to testing using existing circuit testers is disclosed. The chip includes a parallel load instruction which reduces the number of words of tester memory needed to load the internal scan registers. The parallel load instruction loads memory cells connected to the input pins of the chip which are then shifted into the scan registers.

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Cupertino, CA, United States of America

Ross V La Fetra