Nvidia Corporation

Intel Corporation

Synopsys, Inc.

Ross Segelken

Darrell D Boggs

Guillermo Juan Rozas

David A Dunn

Alexander Klaiber

Paul S Serris

Magnus Ekman

Nathan Daniel Tuck

Hens Vanderschoot

Brad Hoyt

Sridharan Ramakrishnan

James Van Zoeren

Madhu Swarna

Aneesh Aggarwal

Ben Hertzberg

Rupert Brauch

Kevin Koschoreck

Paul Wasson

Shailender Chaudhry

Feng Chen

David J Sager

Jeffrey Lee Sonntag

Daniel Keith Weinlader

Yusuf Cagatay Tekmen

Robert Beverly Lefferts

Bruce Holmer

Alex Klaiber

Aravindh Baktha

Christopher Scott Jones

Nickolas Andrew Fortino

Nick Fortino

Mike Cornaby

Thomas Kistler

David Hass

Sean Benton Franey

Samuel Charles Tsen, Jr

Nikhita Kunati

Michael P Cornaby

Polychronis Xekalakis

Denis Khartikov

Aaron Joseph Caffee

Alok Mooley

Gordon Vreugdenhil

Shiaoli Mendyke

A first thread is executed in a first pipeline of a first core of an integrated circuit (IC). The first core includes a first set of hardware structures. A second thread is executed in a second pipeline of a second core of the IC. The second core includes a second set of hardware structures. In response to a command to operate the IC with a unified core, the first core is combined with the second core to obtain the unified core. To unify the first core, the first pipeline is unified with the second pipeline to obtain a unified pipeline, and the first set of hardware structures is unified with the second set of hardware structures to obtain a unified set of hardware structures. A single thread is executed in the unified pipeline of the unified core using the unified set of hardware structures.

Dynamic reconfiguration of a multi-core processor to a unified core

An improved architectural means to address processor cache attacks based on speculative execution defines a new memory type that is both cacheable and inaccessible by speculation. Speculative execution cannot access and expose a memory location that is speculatively inaccessible. Such mechanisms can disqualify certain sensitive data from being exposed through speculative execution. Data which must be protected at a performance cost may be specifically marked. If the processor is told where secrets are stored in memory and is forbidden from speculating on those memory locations, then the processor will ensure the process trying to access those memory locations is privileged to access those locations before reading and caching them. Such countermeasure is effective against attacks that use speculative execution to leak secrets from a processor cache.

Memory type which is cacheable yet inaccessible by speculative instructions

The disclosure provides a method and a system for identifying and replacing code translations that generate spurious fault events. In one embodiment the method includes executing a first set and a second set of native instructions, performing a third translation of a target instruction to form a third set of native instructions in response to a determination that a fault occurrence is attributed to a first translation, wherein the third set of native instructions is not the same as the second set of native instructions, and the third set of native instructions is not the same as the first set of native instructions, and executing the third set of native instructions.

Fault detection in instruction translations

A processing system comprising a microprocessor core and a translator. Within the microprocessor core is arranged a hardware decoder configured to selectively decode instructions for execution in the microprocessor core, and, a logic structure configured to track usage of the hardware decoder. The translator is operatively coupled to the logic structure and configured to selectively translate the instructions for execution in the microprocessor core, based on the usage of the hardware decoder as determined by the logic structure.

Instruction-optimizing processor with branch-count table in hardware

Embodiments related to fetching instructions and alternate versions achieving the same functionality as the instructions from an instruction cache included in a microprocessor are provided. In one example, a method is provided, comprising, at an example microprocessor, fetching an instruction from an instruction cache. The example method also includes hashing an address for the instruction to determine whether an alternate version of the instruction which achieves the same functionality as the instruction exists. The example method further includes, if hashing results in a determination that such an alternate version exists, aborting fetching of the instruction and retrieving and executing the alternate version.

Translation address cache for a microprocessor

The disclosure provides a micro-processing system operable in a hardware decoder mode and in a translation mode. In the hardware decoder mode, the hardware decoder receives and decodes non-native ISA instructions into native instructions for execution in a processing pipeline. In the translation mode, native translations of non-native ISA instructions are executed in the processing pipeline without using the hardware decoder. The system includes a code portion profile stored in hardware that changes dynamically in response to use of the hardware decoder to execute portions of non-native ISA code. The code portion profile is then used to dynamically form new native translations executable in the translation mode.

Profiling code portions to generate translations

Embodiments related to managing lazy runahead operations at a microprocessor are disclosed. For example, an embodiment of a method for operating a microprocessor described herein includes identifying a primary condition that triggers an unresolved state of the microprocessor. The example method also includes identifying a forcing condition that compels resolution of the unresolved state. The example method also includes, in response to identification of the forcing condition, causing the microprocessor to enter a runahead mode.

Lazy runahead operation for a microprocessor

In one embodiment, a micro-processing system includes a hardware structure disposed on a processor core. The hardware structure includes a plurality of entries, each of which are associated with portion of code and a translation of that code which can be executed to achieve substantially equivalent functionality. The hardware structure includes a redirection array that enables, when referenced, execution to be redirected from a portion of code to its counterpart translation. The entries enabling such redirection are maintained within or evicted from the hardware structure based on usage information for the entries.

Improving hit rate of code translation redirection table with replacement strategy based on usage history table of evicted entries

Embodiments related to re-dispatching an instruction selected for re-execution from a buffer upon a microprocessor re-entering a particular execution location after runahead are provided. In one example, a microprocessor is provided. The example microprocessor includes fetch logic, one or more execution mechanisms for executing a retrieved instruction provided by the fetch logic, and scheduler logic for scheduling the retrieved instruction for execution. The example scheduler logic includes a buffer for storing the retrieved instruction and one or more additional instructions, the scheduler logic being configured, upon the microprocessor re-entering at a particular execution location after runahead, to re-dispatch, from the buffer, an instruction that has been previously dispatched to one of the execution mechanisms.

Checkpointed buffer for re-entry from runahead

Various embodiments of microprocessors and methods of operating a microprocessor during runahead operation are disclosed herein. One example method of operating a microprocessor includes identifying a runahead-triggering event associated with a runahead-triggering instruction and, responsive to identification of the runahead-triggering event, entering runahead operation and inserting the runahead-triggering instruction along with one or more additional instructions in a queue. The example method also includes resuming non-runahead operation of the microprocessor in response to resolution of the runahead-triggering event and re-dispatching the runahead-triggering instruction along with the one or more additional instructions from the queue to the execution logic.

Queued instruction re-dispatch after runahead

Embodiments related to managing potentially invalid results generated/obtained by a microprocessor during runahead are provided. In one example, a method for operating a microprocessor includes causing the microprocessor to enter runahead upon detection of a runahead event. The example method also includes, during runahead, determining that an operation associated with an instruction referencing a storage location would produce a potentially invalid result based on a value of an architectural poison bit associated with the storage location and performing a different operation in response.

Managing potentially invalid results during runahead

Various embodiments relating to executing different types of instruction code in a micro-processing system are provided. In one embodiment, a micro-processing system includes a memory/storage subsystem configured to store non-native instruction set architecture (ISA) code and native ISA code in a common address space, fetch logic configured to retrieve the non-native ISA code and native ISA code from the common address space, instruction type determining logic configured to determine, at runtime, whether fetched instruction code is non-native ISA code or native ISA code, and processing logic configured to execute the fetched instruction code via a first pipeline configuration in response to the instruction type determining logic determining that the fetched instruction code is non-native ISA code, and via a second pipeline configuration which is different than the first pipeline configuration, in response to the instruction type determining logic determining that the fetched instruction code is native ISA code.

Dynamic configuration of processing pipeline based on determined type of fetched instruction

In one embodiment, a microprocessor is provided. The microprocessor includes instruction memory and a branch prediction unit. The branch prediction unit is configured to use information from the instruction memory to selectively power up the branch prediction unit from a powered-down state when fetched instruction data includes a branch instruction and maintain the branch prediction unit in the powered-down state when the fetched instruction data does not include a branch instruction in order to reduce power consumption of the microprocessor during instruction fetch operations.

Branch prediction power reduction

In one embodiment, a microprocessor is provided. The microprocessor includes a branch prediction unit. The branch prediction unit is configured to track the presence of branches in instruction data that is fetched from an instruction memory after a redirection at a target of a predicted taken branch. The branch prediction unit is selectively powered up from a powered-down state when the fetched instruction data includes a branch instruction and is maintained in the powered-down state when the fetched instruction data does not include an instruction branch in order to reduce power consumption of the microprocessor during instruction fetch operations.

Growing community of inventors

Portland, OR, United States of America

Ross Segelken