National Instruments Corporation

Silicon Laboratories Inc.

Ross Sabolcik

Robert Wayne Hormuth

Kevin L Schultz

Craig M Conway

Bob Mitchell

Glen Sescila

B Keith Odom

Michael James Mills

Michael L Duffy

Tufan C Karalar

András Vince Horvath

Paulo Santos

Rudye McGlothlin

An apparatus for controlling a high-power drive device external to a package of a motor drive circuit includes a motor drive circuit. The motor drive circuit includes a driver to control the high-power drive device based on a first reference voltage, a second reference voltage, and a control signal based on a received control signal. A fault circuit generates a failure indicator based on a voltage across terminals of the high-power drive device. A fault condition is based on the failure indicator. A first terminal coupled to the driver charges a node of the high-power drive device over a first length of time in response to an absence of the fault condition and a first level of the control signal. A second terminal coupled to the driver discharges the node over a second length of time different from the first length of time.

Soft shutdown for isolated drivers

A Wide Area Serial PCI system for connecting peripheral devices to a computer. The WASP system includes a host computer system connected through a serial bus to a remote device. The serial bus can range from several meters to several kilometers or more. The host computer system includes a CPU and memory, and also includes a first Peripheral Component Interconnect (PCI) bus, also referred to as the local PCI bus. A primary bridge according to the present invention is coupled to the first PCI bus. The primary bridge includes PCI interface circuitry for interfacing to the first PCI bus. The remote device is located remotely from the computer system and comprises a second or remote PCI bus and one or more peripheral devices coupled to the second PCI bus. The remote device also includes a secondary bridge coupled to the second PCI bus. The secondary bridge includes PCI interface circuitry for interfacing to the second PCI bus. The serial bus is coupled between the primary bridge and the secondary bridge. Each of the primary bridge and secondary bridge include parallel/serial transceivers for converting parallel data generated on the first PCI bus and second PCI bus, respectively, to serial data for transmission on the serial bus and for converting serial data received from the serial bus to parallel data for generation on the first PCI bus and second PCI bus, respectively. The primary bridge and the secondary bridge collectively implement a PCI&mdash;PCI bridge register set.

System and method for connecting peripheral buses through a serial bus

System and method for coupling peripheral buses through a serial bus using a split bridge implementation

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Austin, TX, United States of America

Ross Sabolcik