Freescale Semiconductor,inc.

Ross L Patterson

Jayanta Bhadra

Xiushan Feng

An approach is provided in which a computing system retrieves a design description that corresponds to an electronic circuit design. The computing system selects an assertion corresponding to the electronic circuit design, which includes one or more assertion signal identifiers corresponding to one or more description signal points included in the design description. Next, the computing system creates a partitioned region from the design description based upon the description signal points. The computing system compiles and verifies the partitioned region that, in turn, verifies the electronic circuit design.

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Austin, TX, United States of America

Ross L Patterson