Micron Technology Incorporated

Round Rock Research, LLC

Aptina Imaging Corporation

Ross E Dermott

Tyler J Gomm

Aaron M Schoenfeld

Travis E Dirkes

Scott Eugene Smith

Daniel R Loughmiller

Eric A Becker

Johannes Solhusvik

Trygve Willassen

Michael Hartmann

A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refresh operation is provided that includes initiating at least one refresh operation in the memory device, and ceasing generation of an internal clock signal timed with respect to the external clock signal for at least a portion of the time in which at least one refresh operation takes to complete.

Circuit and method for controlling a clock synchronizing circuit for low power refresh operation

An imaging method and apparatus which use a pixel array for capturing images and for measuring ambient light conditions.

Method and apparatus for ambient light detection

A delay locked loop circuit and method of operating the same. The delay locked loop circuit comprises a forward delay path having a variable delay portion and a static delay portion, wherein the static delay portion includes a static delay element, a feedback path for generating a feedback signal responsive to an output signal, and a phase detector for comparing the phase of an input signal and the phase of the feedback signal and for generating a variable control signal for controlling the amount of delay provided by the variable delay portion, wherein the static delay element is activated in response to a static control signal indicative of the variable delay portion being unable to lock the output signal to the input signal. Because of the rules governing Abstracts, this Abstract should not be used to construe the claims.

Delay circuit with reset-based forward path static delay

A timing control circuit for synchronizing an output clock signal with an input clock signal includes a pulse generator, a measure delay array, a measure circuit, and a forward delay array. The pulse generator is configured to receive a delay clock signal generated based on the input clock signal and generate a pulse, the pulse having a falling edge corresponding to a rising edge of the delay clock signal. The measure delay array is coupled to the pulse generator to receive the pulse. The measure circuit is configured to determine a position of the pulse within the measure delay array corresponding to a rising edge of the input clock signal. The forward delay array is configured to receive the input clock signal and delay the input clock signal based on the position determined by the measure circuit to generate the output clock signal. A method for synchronizing an output clock signal with an input clock signal includes receiving a delay clock signal generated based on the input clock signal. A pulse is generated having a falling edge corresponding to a rising edge of the delay clock signal. The pulse is propagated through a measure delay array. A position of the pulse within the measure delay array corresponding to a rising edge of the input clock signal is determined. The input clock signal is delayed based on the position determined by the measure circuit to generate the output clock signal.

Measure-controlled delay circuit with reduced playback error

A method and apparatus to characterize a synchronous device after it is packaged. For synchronous devices, such as SDRAMs implementing a Delay Locked Loop (DLL) to synchronize one signal, such as an external clock signal with a second signal, such as a data signal, a counter is coupled to the phase detector of the DLL to track the entry point of the delay line. The entry point information can be taken over a variety of voltages, temperatures, and frequencies to characterize the DLL. The counter may be located on the synchronous device or external to the device.

Method and apparatus for determining digital delay line entry point

A delay locked loop circuit includes a plurality of delay cells connected in series. Each of the delay cells connects to an input node which provides a clock signal. A shift register selects one of the delay cells to allow the clock signal to enter the selected delay cell and propagate to an output node, such that internal gates of delay cells preceding the selected delay cell are not toggling.

Power reduction for delay locked loop circuits

A method and apparatus is provided for performing a filter control of a delay lock loop circuit. A coarse delay and/or a fine delay are implemented upon a reference signal based upon a phase shift between the reference signal and a feedback signal. A synchronized output signal is generated based upon the coarse delay and the fine delay. The apparatus of the present invention includes a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal. The delay lock loop comprises a filter to provide a filter response to the phase difference. The filter response is capable of providing a coarse delay and/or a fine delay.

Controlling a delay lock loop circuit

A delay circuit that includes a plurality of delay cells connected in series. Each of the delay cells connects to an input node which provides a clock signal. A shift register selects one of the delay cells to allow the clock signal to enter the selected delay cell and propagate to an output node, such that internal gates of delay cells preceding the selected delay cell are not toggling.

Growing community of inventors

Boise, ID, United States of America

Ross E Dermott