Microchip Technology Inc.

Roshan Samuel

Igor Wojewoda

Michael Simmons

Joseph Harry Julicher

Yong Yuenyongsgool

Rodney J Pesavento

Ward Brown

Daniel Arthur Ujvari

Brant Ivey

John Day

Erick Pfeifer

Chintan Desai

Razvan Dochia

Sudhir Bommena

Vijay Dubey

Janmichael Aberouette

Jonathan Brant Ivey

Ward R Brown

An apparatus may include a processor. The apparatus may include a memory communicatively coupled to the processor. The apparatus may include a memory control circuit (MCC). The MCC may be configured to define a protected portion of the memory, wherein the protected portion of the memory is configured for read-only access by the processor, increase a size of the protected portion of the memory, and, after the increase in size of the protected portion of the memory, prevent decreases of the size of the protected portion of the memory.

System with increasing protected storage area and erase protection

A universal asynchronous receiver/transmitter (UART) module is disclosed. The UART module may include an edge detector coupled with a data line of the UART module, wherein the edge detector resets a counter on a rising and a falling edge.

UART with line activity detector

A universal asynchronous receiver/transmitter (UART) interface is disclosed. The UART interface may include a configurable asynchronous receiver and transmitter unit; and a configurable state machine, wherein the state machine allows configuration of the receiver and transmitter unit to support various baud rates and provide for start bit and stop bit configuration, wherein the state machine is further configurable to automatically support a plurality of communication protocols.

UART with automated protocols

A universal asynchronous receiver/transmitter (UART) module is disclosed. The UART module may include a receiver unit being clocked by a programmable receiver clock configured to sample an incoming data signal and comprising a counter clocked by said receiver clock, wherein the counter is reset to start counting with every falling edge of the data signal and to trigger a BRK detection signal if the counter reaches a programmable threshold value.

Independent UART BRK detection

A multi-boot device capable of booting from a plurality of boot devices, each storing a boot image. The multi-boot device determines which boot device to load based on sequence numbers assigned to each of the boot devices. Some embodiments will make this determination using only hardware operations. The multi-boot device compares the sequence numbers of the available boot devices in order to determine the boot image to be loaded. The address of the selected boot image is then mapped to the device's default boot vector. The remaining images are likewise mapped to a secondary boot memory. The device then boots from the default boot vector. The user can change the boot device to be loaded by modifying one or more of the boot sequence numbers. The boot images can be updated without resetting the device by switching execution to and from boot images in the secondary boot memory.

Boot sequencing for multi boot devices

A method for hot swapping program code includes defining a predetermined range of new code from which to execute; identifying from the new code one or more system components which require a reinitialization or reset; reinitializing or resetting the one or more system components; and executing the new code.

Minimizing switchover time in a hot swappable program memory

A cyclic redundancy check (CRC) unit has a programmable CRC engine, a variable buffer memory operable to store k words wherein each word has n-bits, wherein k and n can be varied, and shift logic operable to shift data from the variable buffer memory into the programmable CRC engine.

Programmable cyclic redundancy check CRC unit

A microcontroller with an integrated special instruction processing unit and a programmable cycle state machine. The special instruction processing unit allows offloading of intensive processing of output data and the programmable cycle state machine minimizes the amount of customized, off chip circuitry necessary to connect the microcontroller to an external display.

Microcontroller with integrated graphical processing unit

A programmable cycle state machine interface to a microcontroller comprising a programmable cycle state machine, a first and second data bus, a first and second control output, and a control input for programming the cycle of the state machine. The programmable nature of the state machine allows for design and implementation changes without the need to redesign customized state machine logic on the microcontroller.

Growing community of inventors

Chandler, AZ, United States of America

Roshan Samuel