Texas Instruments Corporation

Roshan J Samuel

Jason Douglas Kridner

Gregory Lee Christison

Brian Jason Karguth

The programmable transition state machine of this invention is designed to allow implementation of hardware capable of increasing the performance of critical encoding and decoding tasks in a microprocessor environment where a required encoding or decoding or machines is not known in advance. The state machine described may also be used in systems that need flexibility to support a wide variety of functions or machines or where a hardwired approach is not useful. This unique state machine processes the state information and the transition from a present state to a next state in CPU-programmable logic.

Programmable transition state machine

The invention describes a baud rate generator for use in a sampled data system. This generator makes possible the sampling of asynchronous digital input data when its baud rate is not known, and does so without the use of phase-locked loop circuitry. The invention uses a digital counter to count the clock intervals between successive transitions in the digital input data. This process is repeated over a period of time sufficient to assure that recognizable recurring data patterns will occur in the data stream. The smallest interval recorded by the counter is captured and is directly related to the required sampling rate.

Self-tuning baud rate generator for UART applications

The 64-bit single cycle fetch method described here relates to a specific 'megastar' core processor employed in a range of new digital signal processor devices. The 'megastar' core incorporates 32-bit memory blocks arranged into separate entities or banks. Because the parent CPU has only three 16-bit buses, a maximum read in one clock cycle through the memory interface would normally be 48-bits. This invention describes an approach for a fetch method involving tapping into the memory bank data at an earlier stage prior to the memory interface. This allows the normal 48-bit fetch to be extended to 64-bits as required for full performance of the numerical processor accelerator and other speed critical operations and functions.

64-bit single cycle fetch scheme for megastar architecture

A state machine interface that can be used with digital devices whose interface characteristics are not known in advance. This interface is completely programmable on a clock-by-clock basis. The interface consists of an output component, which can be either a control register or a data bus, and an input component that can be combined to provide various input/output (I/O) functions. The state machine interface of this invention makes it possible to interface with many type of application devices, whose interface characteristics and/or waveforms may not be identical or are not known at the time a particular state machine is designed.

Growing community of inventors

Richardson, TX, United States of America

Roshan J Samuel